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muhammadaldacher
Analog-Design-of-1.9-GHz-PLL-system muhammadaldacher
14
56
unknown
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This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.
pll matlab veriloga analog-design cadence-virtuoso
Created 2019-07-30
13 commits to master branch, last one about a year ago
medwatt
gmid medwatt
9
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unknown
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Python script for generating lookup tables for the gm/ID design methodology and much more ...
gmid mosfet analog-design digital-design mosfet-transistor circuit-simulation
Created 2022-11-27
20 commits to main branch, last one 7 months ago