4 results found Sort:

lakshmi-sathi
avsdpll_1v8 lakshmi-sathi
42
107
gpl-2.0
13
8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperat...
ic pll asic rtl2gds charge-pump analog-circuit manufacturable phase-detector clock-multiplier intellectual-property
Created 2020-10-28
384 commits to main branch, last one 2 years ago
ZipCPU
dpll ZipCPU
26
91
unknown
10
A collection of phase locked loop (PLL) related projects
pll fpga gplv3 verilog verilator
Created 2017-12-04
26 commits to master branch, last one 5 months ago
pavelmc
Si5351mcu pavelmc
25
59
gpl-3.0
16
Arduino Si5351 library tuned for size and click free.
dds pll vfo co7wt bitx20 si5351 arduino hamradio homebrew click-free
Created 2017-04-10
42 commits to master branch, last one 2 years ago
muhammadaldacher
Analog-Design-of-1.9-GHz-PLL-system muhammadaldacher
12
51
unknown
3
This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.
pll matlab veriloga analog-design cadence-virtuoso
Created 2019-07-30
13 commits to master branch, last one about a year ago