lakshmi-sathi / avsdpll_1v8

8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.

lakshmi-sathi
lakshmi-sathi
Date Created 2020-10-28 (4 years ago)
Commits 384 (last one 3 years ago)
Stargazers 109 (0 this week)
Watchers 13 (0 this week)
Forks 41
License gpl-2.0
Ranking

RepositoryStats indexes 598,732 repositories, of these lakshmi-sathi/avsdpll_1v8 is ranked #278,883 (53rd percentile) for total stargazers, and #167,080 for total watchers.

Other Information

lakshmi-sathi/avsdpll_1v8 has Github issues enabled, there is 1 open issue and 0 closed issues.

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

0 commits on the default branch (main) since jan '22

Inactive

No recent commits to this repository

Yearly Commits

Commits to the default branch (main) per year

Issue History

Languages

We don't have any language data for this repository

It's a mystery

updated: 2024-12-08 @ 04:56am, id: 307860553 / R_kgDOElmUSQ