lakshmi-sathi / avsdpll_1v8

8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.

lakshmi-sathi
lakshmi-sathi
Date Created 2020-10-28 (4 years ago)
Commits 384 (last one 3 years ago)
Stargazers 110 (0 this week)
Watchers 13 (0 this week)
Forks 41
License gpl-2.0
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updated: 2025-02-25 @ 07:44pm, id: 307860553 / R_kgDOElmUSQ