lakshmi-sathi / avsdpll_1v8

8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.

Date Created 2020-10-28 (4 years ago)

Commits 384 (last one 3 years ago)

Stargazers 108 (0 this week)

Watchers 13 (0 this week)

Forks 42

License gpl-2.0

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All Topics

ic pll asic rtl2gds charge-pump analog-circuit manufacturable phase-detector clock-multiplier intellectual-property

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updated: 2024-10-29 @ 10:46pm, id: 307860553 / R_kgDOElmUSQ