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8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperat...
Created 2020-10-28
384 commits to main branch, last one 3 years ago
A pure symbolic circuit analyzer.
Created 2020-09-01
77 commits to master branch, last one 5 months ago
This repo contains the code that runs RL+GNN to optimize LDOs in SKY130 process.
Created 2023-05-10
29 commits to main branch, last one 6 months ago