SpinalHDL / SpinalHDL

Scala based HDL

SpinalHDL
SpinalHDL
Date Created 2015-01-25 (10 years ago)
Commits 7,616 (last one a day ago)
Stargazers 1,763 (3 this week)
Watchers 80 (0 this week)
Forks 342
License other
Ranking

RepositoryStats indexes 637,085 repositories, of these SpinalHDL/SpinalHDL is ranked #30,919 (95th percentile) for total stargazers, and #23,675 for total watchers. Github reports the primary language for this repository as Scala, for repositories using this language it is ranked #94/2,042.

SpinalHDL/SpinalHDL is also tagged with popular topics, for these it's ranked: scala (#82/1004),  fpga (#14/523),  verilog (#12/312)

Other Information

SpinalHDL/SpinalHDL has 32 open pull requests on Github, 704 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 133 open issues and 644 closed issues.

There have been 28 releases, the latest one was published on 2025-04-08 (a day ago) with the name v1.12.1.

All Topics
rtl fpga vhdl scala verilog

Star History

Github stargazers over time

1.8k1.8k1.6k1.6k1.4k1.4k1.2k1.2k1k1k8008006006004004002002000020162016201720172018201820192019202020202021202120222022202320232024202420252025

Watcher History

Github watchers over time, collection started in '23

828280807878767674747272707020232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Recent Commit History

3,569 commits on the default branch (dev) since jan '22

4k4k3.5k3.5k3k3k2.5k2.5k2k2k1.5k1.5k1k1k50050000Jul '22Jul '2220232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Yearly Commits

Commits to the default branch (dev) per year

1.6k1.6k1.4k1.4k1.2k1.2k1k1k80080060060040040020020000201520152016201620172017201820182019201920202020202120212022202220242024

Issue History

Total Issues
Open Issues
Closed Issues
80080070070060060050050040040030030020020010010000201720172018201820192019202020202021202120222022202320232024202420252025

Languages

The primary language is Scala but there's also others...

ScalaScalaVerilogVerilogPythonPythonVHDLVHDLSystemVerilogSystemVerilogC++C++StataStataJavaJavaMakefileMakefileSWIGSWIGOtherOther

updated: 2025-04-08 @ 08:23pm, id: 29812153 / R_kgDOAcbluQ