hughperkins / VeriGPU

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

Date Created 2022-03-01 (2 years ago)

Commits 835 (last one 5 months ago)

Stargazers 828 (6 this week)

Watchers 28 (0 this week)

Forks 93

License mit

Ranking

RepositoryStats indexes 584,353 repositories, of these hughperkins/VeriGPU is ranked #60,911 (90th percentile) for total stargazers, and #81,376 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #11/173.

hughperkins/VeriGPU is also tagged with popular topics, for these it's ranked: machine-learning (#1,508/7926), gpu (#167/900), verilog (#32/282), risc-v (#38/263)

Other Information

hughperkins/VeriGPU has Github issues enabled, there are 11 open issues and 5 closed issues.

All Topics

gpu risc-v verilog asic-design verification risc-v-assembly gpu-acceleration hardware-designs machine-learning

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

835 commits on the default branch (main) since jan '22

Yearly Commits

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Issue History

Languages

The primary language is SystemVerilog but there's also others...

updated: 2024-11-21 @ 05:56am, id: 464853976 / R_kgDOG7Ub2A