hughperkins / VeriGPU

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

Date Created 2022-03-01 (2 years ago)

Commits 841 (last one 29 days ago)

Stargazers 856 (0 this week)

Watchers 30 (0 this week)

Forks 94

License mit

Ranking

RepositoryStats indexes 595,856 repositories, of these hughperkins/VeriGPU is ranked #59,500 (90th percentile) for total stargazers, and #73,272 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #11/178.

hughperkins/VeriGPU is also tagged with popular topics, for these it's ranked: machine-learning (#1,489/8063), gpu (#165/918), verilog (#32/289), risc-v (#38/268)

Other Information

hughperkins/VeriGPU has Github issues enabled, there are 11 open issues and 5 closed issues.

All Topics

gpu risc-v verilog asic-design verification risc-v-assembly gpu-acceleration hardware-designs machine-learning

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

841 commits on the default branch (main) since jan '22

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Languages

The primary language is SystemVerilog but there's also others...

updated: 2024-12-17 @ 09:17pm, id: 464853976 / R_kgDOG7Ub2A