hughperkins / VeriGPU

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

Date Created 2022-03-01 (2 years ago)

Commits 834 (last one 19 days ago)

Stargazers 663 (5 this week)

Watchers 26 (0 this week)

Forks 75

License mit

Ranking

RepositoryStats indexes 528,822 repositories, of these hughperkins/VeriGPU is ranked #69,102 (87th percentile) for total stargazers, and #83,055 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #12/152.

hughperkins/VeriGPU is also tagged with popular topics, for these it's ranked: machine-learning (#1,638/7315), gpu (#193/820), verilog (#35/254), risc-v (#38/224)

Other Information

hughperkins/VeriGPU has Github issues enabled, there are 11 open issues and 5 closed issues.

All Topics

gpu risc-v verilog asic-design verification risc-v-assembly gpu-acceleration hardware-designs machine-learning

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

834 commits on the default branch (main) since jan '22

Yearly Commits

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Issue History

Languages

The primary language is SystemVerilog but there's also others...

updated: 2024-06-12 @ 06:28pm, id: 464853976 / R_kgDOG7Ub2A