KastnerRG / cgra4ml

An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

Date Created 2020-07-12 (4 years ago)

Commits 1,139 (last one about a month ago)

Stargazers 73 (0 this week)

Watchers 0 (0 this week)

Forks 10

License apache-2.0

Ranking

RepositoryStats indexes 628,047 repositories, of these KastnerRG/cgra4ml is ranked #378,552 (40th percentile) for total stargazers, and #622,409 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #109/193.

KastnerRG/cgra4ml is also tagged with popular topics, for these it's ranked: ai (#2,920/4749), neural-network (#824/1134), cnn (#366/570), fpga (#340/508), verilog (#209/305)

Other Information

KastnerRG/cgra4ml has Github issues enabled, there is 1 open issue and 7 closed issues.

All Topics

ai cnn dnn asic fpga hls4ml verilog axi-stream asic-design systemverilog neural-network

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Recent Commit History

630 commits on the default branch (master) since jan '22

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The primary language is SystemVerilog but there's also others...

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updated: 2025-03-14 @ 09:41pm, id: 279006508 / R_kgDOEKFNLA