michaelehab / AES-Verilog

Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL

Date Created 2022-04-30 (2 years ago)

Commits 45 (last one 2 years ago)

Stargazers 85 (1 this week)

Watchers 2 (0 this week)

Forks 20

License unknown

Ranking

RepositoryStats indexes 595,856 repositories, of these michaelehab/AES-Verilog is ranked #328,457 (45th percentile) for total stargazers, and #485,301 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #261/563.

michaelehab/AES-Verilog is also tagged with popular topics, for these it's ranked: security (#2,886/4067), cryptography (#689/1039), encryption (#435/646), fpga (#290/488), verilog (#182/289), learn (#122/229)

Other Information

michaelehab/AES-Verilog has 1 open pull request on Github, 0 pull requests have been merged over the lifetime of the repository.

All Topics

aes rtl fpga learn aes-128 aes-192 aes-256 verilog fpga-soc security encryption fpga-board verilog-hdl cryptography aes-decryption aes-encryption verilog-project encryption-decryption

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Recent Commit History

45 commits on the default branch (main) since jan '22

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Languages

The only known language in this repository is Verilog

updated: 2024-12-19 @ 01:55am, id: 487368446 / R_kgDOHQym_g