michaelehab / AES-Verilog

Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL

Date Created 2022-04-30 (2 years ago)

Commits 45 (last one about a year ago)

Stargazers 55 (0 this week)

Watchers 2 (0 this week)

Forks 14

License unknown

Ranking

RepositoryStats indexes 523,840 repositories, of these michaelehab/AES-Verilog is ranked #399,269 (24th percentile) for total stargazers, and #442,567 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #313/447.

michaelehab/AES-Verilog is also tagged with popular topics, for these it's ranked: security (#3,188/3704), cryptography (#789/939), encryption (#491/583), fpga (#341/425), verilog (#204/251), learn (#145/208)

All Topics

aes rtl fpga learn aes-128 aes-192 aes-256 verilog fpga-soc security encryption fpga-board verilog-hdl cryptography aes-decryption aes-encryption verilog-project encryption-decryption

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

45 commits on the default branch (main) since jan '22

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Languages

The only known language in this repository is Verilog

updated: 2024-05-25 @ 01:28am, id: 487368446 / R_kgDOHQym_g