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一个开源的FPGA神经网络加速器。
Created 2021-09-06
28 commits to main branch, last one about a year ago
Firmware with overclock support for LibreSDR (PlutoSDR clone with Zynq 7020), 27.5 MSPS sample rate over Gigabit Ethernet with libiio/PlutoSDR API
Created 2024-01-03
11 commits to main branch, last one 11 months ago
Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP
Created 2021-06-23
1 commits to main branch, last one 3 years ago
This is xc7z020clg400 FPGA hardware core board design
Created 2023-11-07
3 commits to master branch, last one about a year ago