Teddy-van-Jerry / sdr-psk-fpga

Dual-Mode PSK Transceiver on SDR With FPGA

Date Created 2023-12-07 (about a year ago)

Commits 96 (last one 5 months ago)

Stargazers 28 (0 this week)

Watchers 3 (0 this week)

Forks 13

License mit

Ranking

RepositoryStats indexes 630,443 repositories, of these Teddy-van-Jerry/sdr-psk-fpga is ranked #608,551 (3rd percentile) for total stargazers, and #416,864 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #594/616.

Teddy-van-Jerry/sdr-psk-fpga is also tagged with popular topics, for these it's ranked: fpga (#508/515), verilog (#303/307), sdr (#207/208), synchronization (#180/184)

Other Information

Homepage URL: https://go.wqzhao.org/sdr-psk-fpga

All Topics

amd psk sdr bpsk fpga qpsk zynq vivado xilinx gardner verilog zynq-7000 zynq-7020 modulation costas-loop transceiver demodulation synchronization software-defined-radio

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

96 commits on the default branch (master) since jan '22

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Languages

The primary language is Verilog but there's also others...

updated: 2025-03-19 @ 03:51pm, id: 728575652 / R_kgDOK20upA