chipsalliance / yosys-f4pga-plugins

Plugins for Yosys developed as part of the F4PGA project.

Date Created 2019-11-07 (4 years ago)

Commits 1,466 (last one 5 months ago)

Stargazers 83 (0 this week)

Watchers 18 (0 this week)

Forks 46

License apache-2.0

Ranking

RepositoryStats indexes 535,551 repositories, of these chipsalliance/yosys-f4pga-plugins is ranked #308,596 (42nd percentile) for total stargazers, and #119,848 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #238/461.

chipsalliance/yosys-f4pga-plugins is also tagged with popular topics, for these it's ranked: fpga (#270/435), eda (#84/126)

Other Information

chipsalliance/yosys-f4pga-plugins has 18 open pull requests on Github, 378 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 66 open issues and 55 closed issues.

Homepage URL: https://f4pga.org

All Topics

eda fpga f4pga yosys xilinx toolchain xilinx-fpga yosys-plugin

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Github watchers over time, collection started in '23

Recent Commit History

821 commits on the default branch (main) since jan '22

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Languages

The primary language is Verilog but there's also others...

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updated: 2024-06-24 @ 10:06pm, id: 220229160 / R_kgDODSBuKA