zachjs / sv2v

SystemVerilog to Verilog conversion

Date Created 2019-02-08 (5 years ago)

Commits 1,022 (last one 25 days ago)

Stargazers 564 (3 this week)

Watchers 16 (0 this week)

Forks 55

License bsd-3-clause

Ranking

RepositoryStats indexes 584,353 repositories, of these zachjs/sv2v is ranked #82,659 (86th percentile) for total stargazers, and #137,160 for total watchers. Github reports the primary language for this repository as Haskell, for repositories using this language it is ranked #182/1,444.

zachjs/sv2v is also tagged with popular topics, for these it's ranked: verilog (#49/282)

Other Information

zachjs/sv2v has 2 open pull requests on Github, 15 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 19 open issues and 255 closed issues.

There have been 12 releases, the latest one was published on 2024-05-07 (6 months ago) with the name v0.0.12.

All Topics

yosys verilog conversion systemverilog

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

136 commits on the default branch (master) since jan '22

Yearly Commits

Commits to the default branch (master) per year

Issue History

Languages

The primary language is Haskell but there's also others...

updated: 2024-11-20 @ 04:34pm, id: 169686321 / R_kgDOCh01MQ