SymbiFlow / sphinxcontrib-hdl-diagrams

Sphinx Extension which generates various types of diagrams from Verilog code.

Date Created 2019-10-01 (5 years ago)

Commits 171 (last one about a year ago)

Stargazers 56 (0 this week)

Watchers 16 (0 this week)

Forks 16

License apache-2.0

Ranking

RepositoryStats indexes 595,856 repositories, of these SymbiFlow/sphinxcontrib-hdl-diagrams is ranked #435,441 (27th percentile) for total stargazers, and #137,978 for total watchers. Github reports the primary language for this repository as Python, for repositories using this language it is ranked #83,347/119,431.

SymbiFlow/sphinxcontrib-hdl-diagrams is also tagged with popular topics, for these it's ranked: documentation (#1,076/1316), fpga (#380/488), verilog (#227/289), documentation-tool (#136/159), diagrams (#106/118)

Other Information

SymbiFlow/sphinxcontrib-hdl-diagrams has 2 open pull requests on Github, 50 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 10 open issues and 32 closed issues.

Homepage URL: https://sphinxcontrib-hdl-diagrams.rtfd.io

All Topics

hdl rtl fpga yosys sphinx verilog diagrams symbiflow documentation sphinx-extension documentation-tool

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22 commits on the default branch (main) since jan '22

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updated: 2024-11-25 @ 03:16pm, id: 212140476 / R_kgDODKUBvA