f4pga / prjuray

Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.

Date Created 2020-07-15 (4 years ago)

Commits 28 (last one 2 years ago)

Stargazers 71 (0 this week)

Watchers 19 (0 this week)

Forks 14

License apache-2.0

Ranking

RepositoryStats indexes 595,856 repositories, of these f4pga/prjuray is ranked #371,337 (38th percentile) for total stargazers, and #117,069 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #103/178.

f4pga/prjuray is also tagged with popular topics, for these it's ranked: fpga (#332/488)

Other Information

f4pga/prjuray has 3 open pull requests on Github, 13 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 15 open issues and 6 closed issues.

Homepage URL: https://prjuray.rtfd.io

All Topics

fpga fuzzer vivado xilinx bitstream symbiflow ultrascale xilinx-fpga ultrascale-plus

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Recent Commit History

2 commits on the default branch (master) since jan '22

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Languages

The primary language is SystemVerilog but there's also others...

updated: 2024-10-19 @ 03:23am, id: 279968526 / R_kgDOEK_7Dg