ultraembedded / openlogicbit

Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.

Date Created 2021-06-20 (3 years ago)

Commits 5 (last one 3 years ago)

Stargazers 123 (1 this week)

Watchers 10 (0 this week)

Forks 16

License apache-2.0

Ranking

RepositoryStats indexes 589,134 repositories, of these ultraembedded/openlogicbit is ranked #255,078 (57th percentile) for total stargazers, and #206,941 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #187/549.

ultraembedded/openlogicbit is also tagged with popular topics, for these it's ranked: fpga (#214/482), verilog (#135/284)

Other Information

ultraembedded/openlogicbit has Github issues enabled, there are 2 open issues and 0 closed issues.

All Topics

fpga verilog ftdi232h ftdi2232h altera-fpga xilinx-fpga lattice-fpga logic-analyzer digital-signal-analyzer

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0 commits on the default branch (main) since jan '22

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The primary language is Verilog but there's also others...

updated: 2024-12-03 @ 10:13pm, id: 378749586 / R_kgDOFpNCkg