openhwgroup / cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Date Created 2016-02-18 (8 years ago)

Commits 2,407 (last one 4 months ago)

Stargazers 964 (-1 this week)

Watchers 82 (0 this week)

Forks 421

License other

Ranking

RepositoryStats indexes 585,880 repositories, of these openhwgroup/cv32e40p is ranked #52,501 (91st percentile) for total stargazers, and #22,991 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #8/172.

openhwgroup/cv32e40p is also tagged with popular topics, for these it's ranked: riscv (#25/166)

Other Information

openhwgroup/cv32e40p has 11 open pull requests on Github, 468 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 50 open issues and 435 closed issues.

There have been 21 releases, the latest one was published on 2024-07-15 (4 months ago) with the name cv32e40p_v1.8.3.

Homepage URL: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest

All Topics

riscv riscv32imfc

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

657 commits on the default branch (master) since jan '22

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Issue History

Languages

The primary language is SystemVerilog but there's also others...

updated: 2024-11-23 @ 12:28am, id: 52028445 / R_kgDOAxnkHQ