Wren6991 / Hazard3

3-stage RV32IMACZb* processor with debug

Date Created 2021-05-22 (3 years ago)

Commits 577 (last one about a month ago)

Stargazers 724 (3 this week)

Watchers 20 (0 this week)

Forks 50

License apache-2.0

Ranking

RepositoryStats indexes 589,134 repositories, of these Wren6991/Hazard3 is ranked #68,725 (88th percentile) for total stargazers, and #110,797 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #31/549.

Wren6991/Hazard3 is also tagged with popular topics, for these it's ranked: risc-v (#42/265), riscv (#31/167)

Other Information

Wren6991/Hazard3 has 1 open pull request on Github, 9 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 4 open issues and 13 closed issues.

There have been 4 releases, the latest one was published on 2024-10-12 (about a month ago) with the name v1.0.1.

All Topics

jtag riscv risc-v

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

364 commits on the default branch (stable) since jan '22

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Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2024-12-03 @ 12:35pm, id: 369765988 / R_kgDOFgouZA