Wren6991 / Hazard3

3-stage RV32IMACZb* processor with debug

Date Created 2021-05-22 (3 years ago)
Commits 577 (last one 25 days ago)
Stargazers 701 (0 this week)
Watchers 19 (0 this week)
Forks 48
License apache-2.0
Ranking

RepositoryStats indexes 579,238 repositories, of these Wren6991/Hazard3 is ranked #69,783 (88th percentile) for total stargazers, and #116,113 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #32/533.

Wren6991/Hazard3 is also tagged with popular topics, for these it's ranked: risc-v (#42/261),  riscv (#32/165)

Other Information

Wren6991/Hazard3 has 1 open pull request on Github, 9 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 3 open issues and 11 closed issues.

There have been 4 releases, the latest one was published on 2024-10-12 (25 days ago) with the name v1.0.1.

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Recent Commit History

364 commits on the default branch (stable) since jan '22

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Languages

The primary language is Verilog but there's also others...

updated: 2024-11-05 @ 07:17pm, id: 369765988 / R_kgDOFgouZA