Wren6991 / Hazard3

3-stage RV32IMACZb* processor with debug

Wren6991
Wren6991
Date Created 2021-05-22 (3 years ago)
Commits 579 (last one 26 days ago)
Stargazers 756 (3 this week)
Watchers 20 (0 this week)
Forks 53
License apache-2.0
Ranking

RepositoryStats indexes 600,333 repositories, of these Wren6991/Hazard3 is ranked #67,020 (89th percentile) for total stargazers, and #111,498 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #31/571.

Wren6991/Hazard3 is also tagged with popular topics, for these it's ranked: risc-v (#41/271),  riscv (#31/169)

Other Information

Wren6991/Hazard3 has Github issues enabled, there are 3 open issues and 15 closed issues.

There have been 5 releases, the latest one was published on 2024-12-09 (26 days ago) with the name v1.0.2.

All Topics
jtag riscv risc-v

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Recent Commit History

366 commits on the default branch (stable) since jan '22

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Languages

The primary language is Verilog but there's also others...

updated: 2025-01-04 @ 02:23pm, id: 369765988 / R_kgDOFgouZA