Wren6991 / Hazard3

3-stage RV32IMACZb* processor with debug

Wren6991
Wren6991
Date Created 2021-05-22 (3 years ago)
Commits 579 (last one 3 months ago)
Stargazers 824 (5 this week)
Watchers 21 (0 this week)
Forks 58
License apache-2.0
Ranking

RepositoryStats indexes 630,443 repositories, of these Wren6991/Hazard3 is ranked #63,725 (90th percentile) for total stargazers, and #103,430 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #29/616.

Wren6991/Hazard3 is also tagged with popular topics, for these it's ranked: risc-v (#42/281),  riscv (#31/180)

Other Information

Wren6991/Hazard3 has Github issues enabled, there are 3 open issues and 18 closed issues.

There have been 5 releases, the latest one was published on 2024-12-09 (3 months ago) with the name v1.0.2.

All Topics
jtag riscv risc-v

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

366 commits on the default branch (stable) since jan '22

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Yearly Commits

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Issue History

Total Issues
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Languages

The primary language is Verilog but there's also others...

VerilogVerilogCCC++C++SystemVerilogSystemVerilogPythonPythonMakefileMakefileAssemblyAssemblyShellShellFilebench WMLFilebench WMLFortranFortranOtherOther

updated: 2025-03-24 @ 05:46am, id: 369765988 / R_kgDOFgouZA