Fraunhofer-IMS / airisc_core_complex

Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.

Date Created 2021-12-13 (2 years ago)

Commits 60 (last one 7 months ago)

Stargazers 79 (0 this week)

Watchers 10 (0 this week)

Forks 19

License other

Ranking

RepositoryStats indexes 535,551 repositories, of these Fraunhofer-IMS/airisc_core_complex is ranked #319,043 (40th percentile) for total stargazers, and #199,843 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #244/461.

Fraunhofer-IMS/airisc_core_complex is also tagged with popular topics, for these it's ranked: security (#2,795/3756), ai (#1,931/3144), fpga (#281/435), verilog (#169/257), risc-v (#141/227), embedded-systems (#129/186), riscv (#100/148)

Other Information

Fraunhofer-IMS/airisc_core_complex has Github issues enabled, there is 1 open issue and 2 closed issues.

There have been 3 releases, the latest one was published on 2023-06-02 (about a year ago) with the name v1.3.0.

Homepage URL: https://www.airisc.de

All Topics

ai asic asil fpga riscv risc-v safety verilog security smart-sensors embedded-systems functional-safety

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Recent Commit History

59 commits on the default branch (main) since jan '22

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Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2024-06-28 @ 05:40am, id: 437890229 / R_kgDOGhmstQ