Trending repositories for language Verilog

A Convolutional Neural Network Accelerator implementation on FPGA, xilinx （xczu7ev-ffvc1156-2-i）, The inference of yolov8 took 60ms.

synthesiseable ieee 754 floating point library in verilog

IC implementation of Systolic Array for TPU

This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调试器。

The last Pcileech DMA CFW guide you will ever need. Sponsored by DMAPolice.com

pcileech-fpga with wireless card emulation

3-stage RV32IMACZb* processor with debug

FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog Ethernet components for FPGA implementation

Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward Error Correction coders and decoders Hamming code, Golay code ...

网络训练、图像预处理以及部分hend功能是基于pc端实现的，只有主干网络部署在fpga上，片上资源无法支持整个网络所需资源，建议添加外部存储及DDR

A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA

Affordable 2 GHz 3.2 GS/s 12 bit open-source open-hardware expandable USB oscilloscope

Volumetric Display using an Acoustically Trapped Particle

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and...

Various HDL (Verilog) IP Cores

Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

Verilog PCI express components

Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward Error Correction coders and decoders Hamming code, Golay code ...

A Convolutional Neural Network Accelerator implementation on FPGA, xilinx （xczu7ev-ffvc1156-2-i）, The inference of yolov8 took 60ms.

Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/

IC implementation of Systolic Array for TPU

网络训练、图像预处理以及部分hend功能是基于pc端实现的，只有主干网络部署在fpga上，片上资源无法支持整个网络所需资源，建议添加外部存储及DDR

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

This project utilizes the Digital circuit simulation software,to build a CPU that supports a simple instruction set and simple peripheral circuit simulation. The goal is to support system boot, sta...

This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调试器。

Original FPGA platform

A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA

Affordable 2 GHz 3.2 GS/s 12 bit open-source open-hardware expandable USB oscilloscope

The last Pcileech DMA CFW guide you will ever need. Sponsored by DMAPolice.com

Vortex Graphics

synthesiseable ieee 754 floating point library in verilog

UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.

No description

2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器，支持yolov3-tiny的第一层卷积层计算，可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。

pcileech-fpga with wireless card emulation

🎹 Low-level emulator for SA-synthesis pianos plugin

RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT

A Convolutional Neural Network Accelerator implementation on FPGA, xilinx （xczu7ev-ffvc1156-2-i）, The inference of yolov8 took 60ms.

PicoRV32 - A Size-Optimized RISC-V CPU

No description

FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software

synthesiseable ieee 754 floating point library in verilog

pcileech-fpga with wireless card emulation

Various HDL (Verilog) IP Cores

This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调试器。

Opensource DDR3 Controller

IC implementation of Systolic Array for TPU

Verilog AXI components for FPGA implementation

Verilog Ethernet components for FPGA implementation

The last Pcileech DMA CFW guide you will ever need. Sponsored by DMAPolice.com

32-bit Superscalar RISC-V CPU

Verilog PCI express components

HDL libraries and projects

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

RTL, Cmodel, and testbench for NVDLA

Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit

2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器，支持yolov3-tiny的第一层卷积层计算，可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。

A Convolutional Neural Network Accelerator implementation on FPGA, xilinx （xczu7ev-ffvc1156-2-i）, The inference of yolov8 took 60ms.

A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network

SiliconCompiler Design Gallery

This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调试器。

Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit

Collection of digital hardware modules & projects (benchmarks)

Leaky Integrate and Fire (LIF) model implementation for FPGA

IC implementation of Systolic Array for TPU

网络训练、图像预处理以及部分hend功能是基于pc端实现的，只有主干网络部署在fpga上，片上资源无法支持整个网络所需资源，建议添加外部存储及DDR

Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward Error Correction coders and decoders Hamming code, Golay code ...

2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器，支持yolov3-tiny的第一层卷积层计算，可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。

PCIE 5.0 Graduation project (Verification Team)

An AXI DDR3 SDRAM controller for FPGA

The last Pcileech DMA CFW guide you will ever need. Sponsored by DMAPolice.com

RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.

IC Contest

2023集创赛紫光同创杯一等奖项目

Opensource DDR3 Controller

Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/

A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction

A Convolutional Neural Network Accelerator implementation on FPGA, xilinx （xczu7ev-ffvc1156-2-i）, The inference of yolov8 took 60ms.

efficient anti side channel SHA3 algorithm software and hardware co-design

PicoRV32 - A Size-Optimized RISC-V CPU

FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Affordable 2 GHz 3.2 GS/s 12 bit open-source open-hardware expandable USB oscilloscope

The last Pcileech DMA CFW guide you will ever need. Sponsored by DMAPolice.com

No description

pcileech-fpga with wireless card emulation

Verilog AXI components for FPGA implementation

Verilog Ethernet components for FPGA implementation

Verilog PCI express components

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

RISC-V CPU Core (RV32IM)

The Ultra-Low Power RISC-V Core

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

Open source FPGA-based NIC and platform for in-network compute

This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调试器。

32-bit Superscalar RISC-V CPU

Opensource DDR3 Controller

A Convolutional Neural Network Accelerator implementation on FPGA, xilinx （xczu7ev-ffvc1156-2-i）, The inference of yolov8 took 60ms.

efficient anti side channel SHA3 algorithm software and hardware co-design

Affordable 2 GHz 3.2 GS/s 12 bit open-source open-hardware expandable USB oscilloscope

If you are interested in Digital Hardware Design and/or interested in chip and VLSI design, you may like this repo!

FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.

包含了SOC设计中的通用IP，如外设、总线结构、基础、验证等

The last Pcileech DMA CFW guide you will ever need. Sponsored by DMAPolice.com

This repository houses the ModRetro Chromatic's FPGA design files.

Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/

riscv指令集，单周期以及五级流水线CPU

An AI accelerator implementation with Xilinx FPGA

SiliconCompiler Design Gallery

Collection of digital hardware modules & projects (benchmarks)

This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调试器。

This project utilizes the Digital circuit simulation software,to build a CPU that supports a simple instruction set and simple peripheral circuit simulation. The goal is to support system boot, sta...

RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.

IC Contest

In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.

A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network

网络训练、图像预处理以及部分hend功能是基于pc端实现的，只有主干网络部署在fpga上，片上资源无法支持整个网络所需资源，建议添加外部存储及DDR

Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.

A Convolutional Neural Network Accelerator implementation on FPGA, xilinx （xczu7ev-ffvc1156-2-i）, The inference of yolov8 took 60ms.

DMA-Pcileech-AX200

The last Pcileech DMA CFW guide you will ever need. Sponsored by DMAPolice.com

🎹 Low-level emulator for SA-synthesis pianos plugin

efficient anti side channel SHA3 algorithm software and hardware co-design

No description

Affordable 2 GHz 3.2 GS/s 12 bit open-source open-hardware expandable USB oscilloscope

Amiga Minimig ported to the Tang Nano 20k FPGA

pcileech-fpga with wireless card emulation (D-Link DWA-556 Xtreme N PCIe Desktop Adapter)

CPU Design Based on RISCV ISA

spartan6 blackmagic

包含了SOC设计中的通用IP，如外设、总线结构、基础、验证等

超詳細 ICLAB 2024 Spring 修課心得 & 修課指南，含資源整理

Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples => https://www.chili-chips.xyz/open-cologne | Also see https://na...

artix7 blackmagic

A repo dedicated to create an FPGA implementation of the Philips CD-i

This Repo has Files related to reverse engineering of IBM 98Y2610 Intel Cyclone IV

Emulated firmware for the rtl8188ee

A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network

3-stage RV32IMACZb* processor with debug

PicoRV32 - A Size-Optimized RISC-V CPU

Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.

Verilog Ethernet components for FPGA implementation

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software

No description

Verilog AXI components for FPGA implementation

Open source FPGA-based NIC and platform for in-network compute

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

The Ultra-Low Power RISC-V Core

pcileech-fpga with wireless card emulation

RISC-V CPU Core (RV32IM)

Must-have verilog systemverilog modules

Verilog PCI express components

SERV - The SErial RISC-V CPU

An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-speed...

HDL libraries and projects

Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

An open source GPU based off of the AMD Southern Islands ISA.

Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit

pcileech-fpga with wireless card emulation (D-Link DWA-556 Xtreme N PCIe Desktop Adapter)

efficient anti side channel SHA3 algorithm software and hardware co-design

A tool for synthesizing Verilog programs

An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器

3-stage RV32IMACZb* processor with debug

This repository houses the ModRetro Chromatic's FPGA design files.

FPGA Game Boy Advance for Sipeed Tang boards

Turbo9 - Pipelined 6809 Microprocessor IP

Emulated firmware for the rtl8188ee

东北大学秦皇岛分校-计算机科学与技术专业-资料库

SiliconCompiler Design Gallery

No description

In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.

This repository contains the design files of RISC-V Single Cycle Core

No description

The High-Frequency Trading FPGA System is an ultra-low latency platform for electronic trading on FPGAs. It features a TCP/IP stack, order matching engine, custom IP core, and risk management module f...

An AXI DDR3 SDRAM controller for FPGA

TangMega-138K-example project

Opensource DDR3 Controller