Trending repositories for language Verilog

Verilog Ethernet components for FPGA implementation

A compact USB HID host FPGA core supporting keyboards, mice and gamepads.

PicoRV32 - A Size-Optimized RISC-V CPU

Verilog library for ASIC and FPGA designers

No description

Verilog AXI components for FPGA implementation

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

An open source GPU based off of the AMD Southern Islands ISA.

This repository houses the ModRetro Chromatic's FPGA design files.

No description

Simple 8-bit UART realization on Verilog HDL.

The USRP™ Hardware Driver FPGA Repository

FuseSoC-based SoC for VeeR EH1 and EL2

一步一步写MIPS CPU

32-bit Superscalar RISC-V CPU

Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software

A small, light weight, RISC CPU soft core

Open source FPGA-based NIC and platform for in-network compute

This repository houses the ModRetro Chromatic's FPGA design files.

A compact USB HID host FPGA core supporting keyboards, mice and gamepads.

No description

Simple 8-bit UART realization on Verilog HDL.

The USRP™ Hardware Driver FPGA Repository

FuseSoC-based SoC for VeeR EH1 and EL2

An open source GPU based off of the AMD Southern Islands ISA.

Verilog Ethernet components for FPGA implementation

Verilog library for ASIC and FPGA designers

No description

一步一步写MIPS CPU

Verilog AXI components for FPGA implementation

32-bit Superscalar RISC-V CPU

Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software

PicoRV32 - A Size-Optimized RISC-V CPU

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

A small, light weight, RISC CPU soft core

Open source FPGA-based NIC and platform for in-network compute

PicoRV32 - A Size-Optimized RISC-V CPU

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

This repository houses the ModRetro Chromatic's FPGA design files.

A compact USB HID host FPGA core supporting keyboards, mice and gamepads.

FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software

Verilog AXI components for FPGA implementation

Verilog Ethernet components for FPGA implementation

SD-Card controller, using either SPI, SDIO, or eMMC interfaces

RISC-V CPU Core (RV32IM)

数字逻辑期末大作业，7k下落式音乐游戏

DMA-Pcileech-AX200

32-bit Superscalar RISC-V CPU

Verilog library for ASIC and FPGA designers

No description

The Ultra-Low Power RISC-V Core

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

No description

XBOX 360 advanced glitching - Reverse Engineered using a logic analyzer.

Verilog HDL files

HDL libraries and projects

This repository houses the ModRetro Chromatic's FPGA design files.

数字逻辑期末大作业，7k下落式音乐游戏

TJ-数字逻辑大作业。基于Vivado平台、Verilog语言编写、VGA，mp3，键盘作为外设的接木块游戏。同济大学数字逻辑大作业

A compact USB HID host FPGA core supporting keyboards, mice and gamepads.

No description

In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.

XBOX 360 advanced glitching - Reverse Engineered using a logic analyzer.

Verilog HDL files

Simple 8-bit UART realization on Verilog HDL.

hardware design of universal NPU(CNN accelerator) for various convolution neural network

DMA-Pcileech-AX200

DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3

NES emulator for Xilinx KV260 FPGA board

IC Verification & SV Demo

Microsoft Catapult FPGA, Catapult V3, PCIE Test Demo, On-board usb Blaster and OpenCL BSP

This Repo has Files related to reverse engineering of IBM 98Y2610 Intel Cyclone IV

No description

Affordable 2 GHz 3.2 GS/s 12 bit open-source open-hardware expandable USB oscilloscope

A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA

基于FPGA进行车牌识别

This Repo has Files related to reverse engineering of IBM 98Y2610 Intel Cyclone IV

This repository houses the ModRetro Chromatic's FPGA design files.

XBOX 360 advanced glitching - Reverse Engineered using a logic analyzer.

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software

This Repo has Files related to reverse engineering of IBM 98Y2610 Intel Cyclone IV

The Ultra-Low Power RISC-V Core

Verilog AXI components for FPGA implementation

Verilog Ethernet components for FPGA implementation

Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.

3-stage RV32IMACZb* processor with debug

No description

32-bit Superscalar RISC-V CPU

An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-speed...

Open source FPGA-based NIC and platform for in-network compute

2024年全国大学生嵌入式芯片与系统设计竞赛 FPGA创新设计赛道 国一+易灵思创新杯获奖作品 Ultra-Vision （基于Ti60F225的无极缩放算法实现）

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

HDL libraries and projects

This repository houses the ModRetro Chromatic's FPGA design files.

Verilog library for ASIC and FPGA designers

The last Pcileech DMA CFW guide you will ever need.

A small, light weight, RISC CPU soft core

This repository houses the ModRetro Chromatic's FPGA design files.

XBOX 360 advanced glitching - Reverse Engineered using a logic analyzer.

2024年全国大学生嵌入式芯片与系统设计竞赛 FPGA创新设计赛道 国一+易灵思创新杯获奖作品 Ultra-Vision （基于Ti60F225的无极缩放算法实现）

TJ-数字逻辑大作业。基于Vivado平台、Verilog语言编写、VGA，mp3，键盘作为外设的接木块游戏。同济大学数字逻辑大作业

数字逻辑期末大作业，7k下落式音乐游戏

Affordable 2 GHz 3.2 GS/s 12 bit open-source open-hardware expandable USB oscilloscope

High Speed Data Acquisition over HDMI - FPGA implementation

The last Pcileech DMA CFW guide you will ever need.

超詳細 ICLAB 2024 Spring 修課心得 & 修課指南，含資源整理

同济大学数字逻辑综合作业

DMA Firmware

同济大学22级数字逻辑大作业

TongjiUniversity的一些课程作业

A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPG...

In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.

artix7 blackmagic

Emulated firmware for the rtl8188ee

This project utilizes the Digital circuit simulation software,to build a CPU that supports a simple instruction set and simple peripheral circuit simulation. The goal is to support system boot, sta...

Verilog implementation of PAL, NTSC and SECAM color encoding

An AXI DDR3 SDRAM controller for FPGA

Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.

DMA-Pcileech-AX200

The last Pcileech DMA CFW guide you will ever need.

Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit

Amiga Minimig ported to the Tang Nano 20k FPGA

pcileech-fpga with wireless card emulation (D-Link DWA-556 Xtreme N PCIe Desktop Adapter)

CPU Design Based on RISCV ISA

GPGPU supporting RISCV-V, developed with verilog HDL

2023集创赛紫光同创杯一等奖项目

No description

The High-Frequency Trading FPGA System is an ultra-low latency platform for electronic trading on FPGAs. It features a TCP/IP stack, order matching engine, custom IP core, and risk management module f...

spartan6 blackmagic

A repo dedicated to create an FPGA implementation of the Philips CD-i

Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)

Affordable 2 GHz 3.2 GS/s 12 bit open-source open-hardware expandable USB oscilloscope

This Repo has Files related to reverse engineering of IBM 98Y2610 Intel Cyclone IV

artix7 blackmagic

Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference for understanding and implementing robust clock domain crossing ...

No description

Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples => https://www.chili-chips.xyz/open-cologne | Also see https://na...

3-stage RV32IMACZb* processor with debug

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog Ethernet components for FPGA implementation

Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.

PicoRV32 - A Size-Optimized RISC-V CPU

FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software

Verilog AXI components for FPGA implementation

Open source FPGA-based NIC and platform for in-network compute

No description

The Ultra-Low Power RISC-V Core

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Must-have verilog systemverilog modules

Verilog PCI express components

pcileech-fpga with wireless card emulation

RISC-V CPU Core (RV32IM)

SERV - The SErial RISC-V CPU

HDL libraries and projects

An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-speed...

Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

An open source GPU based off of the AMD Southern Islands ISA.

pcileech-fpga with wireless card emulation (D-Link DWA-556 Xtreme N PCIe Desktop Adapter)

3-stage RV32IMACZb* processor with debug

Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)

Turbo9 - Pipelined 6809 Microprocessor IP

An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器

Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference for understanding and implementing robust clock domain crossing ...

TangMega-138K-example project

No description

In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.

This repository houses the ModRetro Chromatic's FPGA design files.

hardware design of universal NPU(CNN accelerator) for various convolution neural network

No description

Opensource DDR3 Controller

An AXI DDR3 SDRAM controller for FPGA

pcileech-fpga with wireless card emulation

Emulated firmware for the rtl8188ee

No description

MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design

You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size of the systolic array can be changed, now it is 16X16.

TJ-数字逻辑大作业。基于Vivado平台、Verilog语言编写、VGA，mp3，键盘作为外设的接木块游戏。同济大学数字逻辑大作业