Trending repositories for language Verilog

FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software

DMA-KillerWiFI-CFW-BYPASS

Opensource DDR3 Controller

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product ...

No description

tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.

This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design

This repo contains code snippets written in verilog as part of course Computer Architecture of my university curriculum

The last DMA CFW guide you will ever need.

基于FPGA进行车牌识别

The High-Frequency Trading FPGA System is an ultra-low latency platform for electronic trading on FPGAs. It features a TCP/IP stack, order matching engine, custom IP core, and risk management module f...

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

FPGA exercise for beginners

Reference design for Lattice ECP5 FPGA. Featuring Raspberry Pi interface and 6 PMODs

Verilog based BCH encoder/decoder

OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.

OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.

通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器

A full-speed device-side USB peripheral core written in Verilog.

FPGA cores compatible with multiple arcade game machines and KiCAD schematics of arcade games. Working on MiSTer FPGA/Analogue Pocket

No description

tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.

DMA-KillerWiFI-CFW-BYPASS

This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design

This repo contains code snippets written in verilog as part of course Computer Architecture of my university curriculum

The last DMA CFW guide you will ever need.

基于FPGA进行车牌识别

The High-Frequency Trading FPGA System is an ultra-low latency platform for electronic trading on FPGAs. It features a TCP/IP stack, order matching engine, custom IP core, and risk management module f...

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

FPGA exercise for beginners

Reference design for Lattice ECP5 FPGA. Featuring Raspberry Pi interface and 6 PMODs

Opensource DDR3 Controller

Verilog based BCH encoder/decoder

OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product ...

OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.

通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器

A full-speed device-side USB peripheral core written in Verilog.

FPGA cores compatible with multiple arcade game machines and KiCAD schematics of arcade games. Working on MiSTer FPGA/Analogue Pocket

xkISP：Xinkai ISP IP Core (HLS)

No description

FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software

DMA-KillerWiFI-CFW-BYPASS

Opensource DDR3 Controller

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product ...

No description

tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.

This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design

This repo contains code snippets written in verilog as part of course Computer Architecture of my university curriculum

The last DMA CFW guide you will ever need.

基于FPGA进行车牌识别

The High-Frequency Trading FPGA System is an ultra-low latency platform for electronic trading on FPGAs. It features a TCP/IP stack, order matching engine, custom IP core, and risk management module f...

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

FPGA exercise for beginners

Reference design for Lattice ECP5 FPGA. Featuring Raspberry Pi interface and 6 PMODs

Verilog based BCH encoder/decoder

OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.

OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.

通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器

A full-speed device-side USB peripheral core written in Verilog.

No description

No description

tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.

DMA-KillerWiFI-CFW-BYPASS

This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design

This repo contains code snippets written in verilog as part of course Computer Architecture of my university curriculum

The last DMA CFW guide you will ever need.

基于FPGA进行车牌识别

The High-Frequency Trading FPGA System is an ultra-low latency platform for electronic trading on FPGAs. It features a TCP/IP stack, order matching engine, custom IP core, and risk management module f...

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

FPGA exercise for beginners

Reference design for Lattice ECP5 FPGA. Featuring Raspberry Pi interface and 6 PMODs

Opensource DDR3 Controller

Verilog based BCH encoder/decoder

OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product ...

OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.

通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器

A full-speed device-side USB peripheral core written in Verilog.

FPGA cores compatible with multiple arcade game machines and KiCAD schematics of arcade games. Working on MiSTer FPGA/Analogue Pocket

DMA-KillerWiFI-CFW-BYPASS

FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog Ethernet components for FPGA implementation

Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

pcileech-fpga with wireless card emulation

The Ultra-Low Power RISC-V Core

Open source FPGA-based NIC and platform for in-network compute

PicoRV32 - A Size-Optimized RISC-V CPU

Verilog AXI components for FPGA implementation

The last DMA CFW guide you will ever need.

Verilog PCI express components

3-stage RV32IMACZb* processor with debug

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器...

SERV - The SErial RISC-V CPU

No description

HDL libraries and projects

Must-have verilog systemverilog modules

RISC-V CPU Core (RV32IM)

The last DMA CFW guide you will ever need.

DMA-KillerWiFI-CFW-BYPASS

No description

超詳細 ICLAB 2024 Spring 修課心得 & 修課指南，含資源整理

shadow+writemask for all caps. has WORKING logic for interrupts, but not this specific device. DONT BUY FROM DMANATION.

pcileech-fpga with wireless card emulation (D-Link DWA-556 Xtreme N PCIe Desktop Adapter)

Emulated firmware for the rtl8188ee

A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network

hardware design of universal NPU(CNN accelerator) for various convolution neural network

Reverse-engineering of SEGA chips

2022年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛紫光同创赛道视频色度亮度提取赛题设计源文件

This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design

DivTIESUS is a SD/MMC interface for the ZX Spectrum, compatible with ESXDOS. It is not a clone of Mario Pratto's DivMMC.

MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design

pcileech-fpga with wireless card emulation

DMA Firmware

spartan6 blackmagic

Spring 2023 NYCU (prev. NCTU) Integrated Circuit Design Laboratory (ICLab)

An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器

Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.

Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.

No description

DMA-KillerWiFI-CFW-BYPASS

Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit

Amiga Minimig ported to the Tang Nano 20k FPGA

pcileech-fpga with wireless card emulation (D-Link DWA-556 Xtreme N PCIe Desktop Adapter)

CPU Design Based on RISCV ISA

2023集创赛紫光同创杯一等奖项目

GPGPU supporting RISCV-V, developed with verilog HDL

No description

The High-Frequency Trading FPGA System is an ultra-low latency platform for electronic trading on FPGAs. It features a TCP/IP stack, order matching engine, custom IP core, and risk management module f...

The last DMA CFW guide you will ever need.

Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)

spartan6 blackmagic

The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the FPGA can be monitored in a waveform.

A repo dedicated to create an FPGA implementation of the Philips CD-i

Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference for understanding and implementing robust clock domain crossing ...

No description

Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples. https://www.chili-chips.xyz/open-cologne

building blocks for accelerating ZK proofs over binary fields

3-stage RV32IMACZb* processor with debug

Z80 open-source silicon clone. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.

Verilog Ethernet components for FPGA implementation

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

PicoRV32 - A Size-Optimized RISC-V CPU

FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software

Verilog AXI components for FPGA implementation

Open source FPGA-based NIC and platform for in-network compute

No description

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Must-have verilog systemverilog modules

Verilog PCI express components

An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器...

All in one vscode plugin for HDL development

The Ultra-Low Power RISC-V Core

SERV - The SErial RISC-V CPU

RISC-V CPU Core (RV32IM)

HDL libraries and projects

pcileech-fpga with wireless card emulation

Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

Turbo9 - Pipelined 6809 Microprocessor IP

pcileech-fpga with wireless card emulation (D-Link DWA-556 Xtreme N PCIe Desktop Adapter)

The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the FPGA can be monitored in a waveform.

3-stage RV32IMACZb* processor with debug

Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)

An open-source benchmark for generating design RTL with natural language

An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器

No description

hardware design of universal NPU(CNN accelerator) for various convolution neural network

Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference for understanding and implementing robust clock domain crossing ...

pcileech-fpga with wireless card emulation

TangMega-138K-example project

A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA

Opensource DDR3 Controller

FPGA exercise for beginners

This repository contains the design files of RISC-V Pipeline Core

A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction

No description

You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size of the systolic array can be changed, now it is 16X16.

Spring 2023 NYCU (prev. NCTU) Integrated Circuit Design Laboratory (ICLab)