Slamy / CDi_MiSTer

A repo dedicated to create an FPGA implementation of the Philips CD-i

Slamy
Slamy
Date Created 2024-07-08 (8 months ago)
Commits 95 (last one 8 days ago)
Stargazers 61 (0 this week)
Watchers 8 (0 this week)
Forks 4
License gpl-3.0
Ranking

RepositoryStats indexes 632,768 repositories, of these Slamy/CDi_MiSTer is ranked #430,099 (32nd percentile) for total stargazers, and #237,675 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #365/618.

Other Information

Slamy/CDi_MiSTer has Github issues enabled, there are 2 open issues and 0 closed issues.

Star History

Github stargazers over time

707060605050404030302020101000Aug '24Aug '24Sep '24Sep '24Oct '24Oct '24Nov '24Nov '24Dec '24Dec '2420252025Feb '25Feb '25Mar '25Mar '25

Watcher History

Github watchers over time, collection started in '23

887.57.5776.56.5665.55.555Sep '24Sep '24Oct '24Oct '24Nov '24Nov '24Dec '24Dec '2420252025Feb '25Feb '25Mar '25Mar '25

Recent Commit History

95 commits on the default branch (main) since jan '22

10010090908080707060605050404030302020101000Aug '24Aug '24Sep '24Sep '24Oct '24Oct '24Nov '24Nov '24Dec '24Dec '2420252025Feb '25Feb '25Mar '25Mar '25

Yearly Commits

Commits to the default branch (main) per year

70706060505040403030202010100020242024

Issue History

Total Issues
Open Issues
Closed Issues
2222111111000016 Feb16 Feb24 Feb24 FebMar '25Mar '2508 Mar08 Mar16 Mar16 Mar24 Mar24 Mar

Languages

The primary language is Verilog but there's also others...

VerilogVerilogSystemVerilogSystemVerilogVHDLVHDLC++C++AssemblyAssemblyTclTclStataStataCCShellShellBatchfileBatchfileOtherOther

updated: 2025-03-22 @ 02:30pm, id: 825878819 / R_kgDOMTnpIw