alexforencich / verilog-pcie

Verilog PCI express components

Date Created 2019-01-08 (6 years ago)
Commits 580 (last one 11 months ago)
Stargazers 1,261 (3 this week)
Watchers 53 (0 this week)
Forks 327
License mit
Ranking

RepositoryStats indexes 637,085 repositories, of these alexforencich/verilog-pcie is ranked #43,324 (93rd percentile) for total stargazers, and #38,659 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #18/629.

Other Information

alexforencich/verilog-pcie has 3 open pull requests on Github, 2 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 33 open issues and 22 closed issues.

Star History

Github stargazers over time

1.4k1.4k1.2k1.2k1k1k80080060060040040020020000202020202021202120222022202320232024202420252025

Watcher History

Github watchers over time, collection started in '23

545452525050484846464444424220232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Recent Commit History

162 commits on the default branch (master) since jan '22

180180160160140140120120100100808060604040202000Jul '22Jul '2220232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Yearly Commits

Commits to the default branch (master) per year

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Issue History

Total Issues
Open Issues
Closed Issues
60605050404030302020101000202020202021202120222022202320232024202420252025

Languages

The primary language is Verilog but there's also others...

VerilogVerilogPythonPythonTclTclMakefileMakefileCCShellShell

updated: 2025-04-10 @ 03:51am, id: 164569208 / R_kgDOCc8geA