alexforencich / verilog-pcie

Verilog PCI express components

Date Created 2019-01-08 (5 years ago)
Commits 580 (last one 6 months ago)
Stargazers 1,130 (0 this week)
Watchers 52 (0 this week)
Forks 300
License mit
Ranking

RepositoryStats indexes 579,555 repositories, of these alexforencich/verilog-pcie is ranked #45,212 (92nd percentile) for total stargazers, and #39,498 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #19/533.

Other Information

alexforencich/verilog-pcie has 2 open pull requests on Github, 2 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 30 open issues and 21 closed issues.

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

162 commits on the default branch (master) since jan '22

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Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2024-11-05 @ 10:33pm, id: 164569208 / R_kgDOCc8geA