alexforencich / verilog-pcie

Verilog PCI express components

Date Created 2019-01-08 (5 years ago)
Commits 580 (last one 2 months ago)
Stargazers 1,009 (6 this week)
Watchers 50 (0 this week)
Forks 273
License mit
Ranking

RepositoryStats indexes 535,551 repositories, of these alexforencich/verilog-pcie is ranked #47,928 (91st percentile) for total stargazers, and #40,897 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #19/461.

Other Information

alexforencich/verilog-pcie has 2 open pull requests on Github, 2 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 28 open issues and 20 closed issues.

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

162 commits on the default branch (master) since jan '22

Yearly Commits

Commits to the default branch (master) per year

Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2024-07-03 @ 07:20am, id: 164569208 / R_kgDOCc8geA