merldsu / RISCV_Single_Cycle_Core

This repository contains the design files of RISC-V Single Cycle Core

merldsu
merldsu
Date Created 2023-03-25 (2 years ago)
Commits 14 (last one about a year ago)
Stargazers 36 (1 this week)
Watchers 1 (0 this week)
Forks 8
License apache-2.0
Ranking

RepositoryStats indexes 632,768 repositories, of these merldsu/RISCV_Single_Cycle_Core is ranked #568,245 (10th percentile) for total stargazers, and #556,814 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #550/618.

Other Information

There have been 1 release, the latest one was published on 2023-03-25 (2 years ago) with the name RISC-V Single Cycle Core.

Star History

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

14 commits on the default branch (main) since jan '22

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Issue History

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Languages

The only known language in this repository is Verilog

VerilogVerilog

updated: 2025-03-26 @ 10:40am, id: 618695027 / R_kgDOJOCJcw