chili-chips-ba / openCologne

Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples. https://www.chili-chips.xyz/open-cologne

Date Created 2024-05-09 (6 months ago)

Commits 350 (last one 19 days ago)

Stargazers 46 (1 this week)

Watchers 16 (0 this week)

Forks 2

License bsd-3-clause

Ranking

RepositoryStats indexes 584,353 repositories, of these chili-chips-ba/openCologne is ranked #483,219 (17th percentile) for total stargazers, and #137,160 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #421/535.

chili-chips-ba/openCologne is also tagged with popular topics, for these it's ranked: design (#582/656), embedded (#592/655), fpga (#417/478), risc-v (#219/263), hls (#227/250), pcb (#183/229)

Other Information

chili-chips-ba/openCologne has Github issues enabled, there are 13 open issues and 30 closed issues.

Homepage URL: https://nlnet.nl/project/openCologne

All Topics

hls pcb rtl soc fpga design risc-v digital embedded gatemate colognechip systemverilog

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

350 commits on the default branch (main) since jan '22

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Languages

The primary language is Verilog but there's also others...

updated: 2024-11-20 @ 02:23pm, id: 798146281 / R_kgDOL5K-6Q