alexforencich / verilog-axi

Verilog AXI components for FPGA implementation

alexforencich
alexforencich
Date Created 2018-07-30 (6 years ago)
Commits 188 (last one about a month ago)
Stargazers 1,673 (6 this week)
Watchers 52 (0 this week)
Forks 481
License mit
Ranking

RepositoryStats indexes 637,085 repositories, of these alexforencich/verilog-axi is ranked #32,601 (95th percentile) for total stargazers, and #39,516 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #10/629.

Other Information

alexforencich/verilog-axi has 9 open pull requests on Github, 0 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 53 open issues and 22 closed issues.

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

14 commits on the default branch (master) since jan '22

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Yearly Commits

Commits to the default branch (master) per year

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Issue History

Total Issues
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Closed Issues
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Languages

The primary language is Verilog but there's also others...

VerilogVerilogPythonPythonMakefileMakefileTclTcl

updated: 2025-04-10 @ 08:28am, id: 142810315 / R_kgDOCIMcyw