alexforencich / verilog-axi

Verilog AXI components for FPGA implementation

alexforencich
alexforencich
Date Created 2018-07-30 (5 years ago)
Commits 187 (last one about a year ago)
Stargazers 1,353 (2 this week)
Watchers 52 (0 this week)
Forks 415
License mit
Ranking

RepositoryStats indexes 534,880 repositories, of these alexforencich/verilog-axi is ranked #36,510 (93rd percentile) for total stargazers, and #39,101 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #11/459.

Other Information

alexforencich/verilog-axi has 7 open pull requests on Github, 0 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 44 open issues and 22 closed issues.

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Recent Commit History

13 commits on the default branch (master) since jan '22

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Languages

The primary language is Verilog but there's also others...

updated: 2024-06-30 @ 11:19am, id: 142810315 / R_kgDOCIMcyw