metr0jw / Spiking-Neural-Network-on-FPGA

Leaky Integrate and Fire (LIF) model implementation for FPGA

Date Created 2023-01-17 (2 years ago)
Commits 18 (last one about a year ago)
Stargazers 54 (0 this week)
Watchers 2 (0 this week)
Forks 4
License mit
Ranking

RepositoryStats indexes 616,861 repositories, of these metr0jw/Spiking-Neural-Network-on-FPGA is ranked #457,659 (26th percentile) for total stargazers, and #493,533 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #398/601.

metr0jw/Spiking-Neural-Network-on-FPGA is also tagged with popular topics, for these it's ranked: verilog (#241/299)

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

18 commits on the default branch (main) since jan '22

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Yearly Commits

Commits to the default branch (main) per year

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Issue History

No issues have been posted

Languages

The only known language in this repository is Verilog

VerilogVerilog

updated: 2025-02-11 @ 08:56pm, id: 589877152 / R_kgDOIyjPoA