metr0jw / Spiking-Neural-Network-on-FPGA

Leaky Integrate and Fire (LIF) model implementation for FPGA

Date Created 2023-01-17 (about a year ago)

Commits 18 (last one about a year ago)

Stargazers 47 (0 this week)

Watchers 2 (0 this week)

Forks 4

License mit

Ranking

RepositoryStats indexes 595,856 repositories, of these metr0jw/Spiking-Neural-Network-on-FPGA is ranked #485,516 (19th percentile) for total stargazers, and #485,301 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #428/563.

metr0jw/Spiking-Neural-Network-on-FPGA is also tagged with popular topics, for these it's ranked: verilog (#248/289)

All Topics

snn verilog lif-model lif-neuron verilog-hdl neuromorphic-computing spiking-neural-network spiking-neural-networks computational-neuroscience leaky-integrate-and-fire-model leaky-integrate-and-fire-neuron

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Recent Commit History

18 commits on the default branch (main) since jan '22

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Languages

The only known language in this repository is Verilog

updated: 2024-11-27 @ 03:07pm, id: 589877152 / R_kgDOIyjPoA