alexforencich / verilog-ethernet

Verilog Ethernet components for FPGA implementation

alexforencich
alexforencich
Date Created 2014-11-19 (10 years ago)
Commits 1,202 (last one 10 months ago)
Stargazers 2,372 (5 this week)
Watchers 119 (0 this week)
Forks 713
License mit
Ranking

RepositoryStats indexes 599,932 repositories, of these alexforencich/verilog-ethernet is ranked #21,806 (96th percentile) for total stargazers, and #14,394 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #3/568.

Other Information

alexforencich/verilog-ethernet has 19 open pull requests on Github, 0 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 107 open issues and 64 closed issues.

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Recent Commit History

217 commits on the default branch (master) since jan '22

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Languages

The primary language is Verilog but there's also others...

updated: 2025-01-02 @ 12:45pm, id: 26883874 / R_kgDOAZo3Ig