alexforencich / verilog-ethernet

Verilog Ethernet components for FPGA implementation

alexforencich
alexforencich
Date Created 2014-11-19 (9 years ago)
Commits 1,202 (last one 7 months ago)
Stargazers 2,225 (18 this week)
Watchers 116 (0 this week)
Forks 688
License mit
Ranking

RepositoryStats indexes 565,600 repositories, of these alexforencich/verilog-ethernet is ranked #22,486 (96th percentile) for total stargazers, and #14,876 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #3/505.

Other Information

alexforencich/verilog-ethernet has 18 open pull requests on Github, 0 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 100 open issues and 63 closed issues.

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Recent Commit History

217 commits on the default branch (master) since jan '22

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Languages

The primary language is Verilog but there's also others...

updated: 2024-09-30 @ 07:08am, id: 26883874 / R_kgDOAZo3Ig