alexforencich / verilog-ethernet

Verilog Ethernet components for FPGA implementation

alexforencich
alexforencich
Date Created 2014-11-19 (10 years ago)
Commits 1,203 (last one 24 days ago)
Stargazers 2,483 (8 this week)
Watchers 117 (0 this week)
Forks 738
License mit
Ranking

RepositoryStats indexes 630,459 repositories, of these alexforencich/verilog-ethernet is ranked #21,475 (97th percentile) for total stargazers, and #14,655 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #3/615.

Other Information

alexforencich/verilog-ethernet has 20 open pull requests on Github, 0 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 113 open issues and 66 closed issues.

Star History

Github stargazers over time

2.5k2.5k2k2k1.5k1.5k1k1k5005000020162016201720172018201820192019202020202021202120222022202320232024202420252025

Watcher History

Github watchers over time, collection started in '23

1201201151151101101051051001009595909020232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Recent Commit History

218 commits on the default branch (master) since jan '22

250250200200150150100100505000Jul '22Jul '2220232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Yearly Commits

Commits to the default branch (master) per year

20020018018016016014014012012010010080806060404020200020142014201520152016201620172017201820182019201920202020202120212022202220242024

Issue History

Total Issues
Open Issues
Closed Issues
180180160160140140120120100100808060604040202000201720172018201820192019202020202021202120222022202320232024202420252025

Languages

The primary language is Verilog but there's also others...

VerilogVerilogPythonPythonTclTclMakefileMakefileShellShell

updated: 2025-03-23 @ 10:16pm, id: 26883874 / R_kgDOAZo3Ig