alexforencich / verilog-ethernet

Verilog Ethernet components for FPGA implementation

alexforencich
alexforencich
Date Created 2014-11-19 (9 years ago)
Commits 1,202 (last one 8 months ago)
Stargazers 2,292 (3 this week)
Watchers 116 (0 this week)
Forks 699
License mit
Ranking

RepositoryStats indexes 579,238 repositories, of these alexforencich/verilog-ethernet is ranked #22,140 (96th percentile) for total stargazers, and #14,764 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #3/533.

Other Information

alexforencich/verilog-ethernet has 19 open pull requests on Github, 0 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 104 open issues and 64 closed issues.

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

217 commits on the default branch (master) since jan '22

Yearly Commits

Commits to the default branch (master) per year

Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2024-11-06 @ 09:27pm, id: 26883874 / R_kgDOAZo3Ig