lauchinyuan / FPGA_DDR3_Ctrl

An AXI DDR3 SDRAM controller for FPGA

Date Created 2023-09-17 (about a year ago)
Commits 28 (last one about a year ago)
Stargazers 28 (0 this week)
Watchers 2 (0 this week)
Forks 6
License unknown
Ranking

RepositoryStats indexes 600,333 repositories, of these lauchinyuan/FPGA_DDR3_Ctrl is ranked #581,997 (3rd percentile) for total stargazers, and #488,054 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #557/571.

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Watcher History

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Recent Commit History

28 commits on the default branch (master) since jan '22

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No issues have been posted

Languages

The primary language is Verilog but there's also others...

updated: 2025-01-02 @ 01:09am, id: 692741072 / R_kgDOKUpj0A