lauchinyuan / FPGA_DDR3_Ctrl

An AXI DDR3 SDRAM controller for FPGA

lauchinyuan
lauchinyuan
Date Created 2023-09-17 (about a year ago)
Commits 28 (last one about a year ago)
Stargazers 33 (1 this week)
Watchers 2 (0 this week)
Forks 6
License unknown
Ranking

RepositoryStats indexes 632,768 repositories, of these lauchinyuan/FPGA_DDR3_Ctrl is ranked #585,210 (8th percentile) for total stargazers, and #481,481 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #565/618.

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

28 commits on the default branch (master) since jan '22

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Yearly Commits

Commits to the default branch (master) per year

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Issue History

No issues have been posted

Languages

The primary language is Verilog but there's also others...

VerilogVerilogMATLABMATLABTclTcl

updated: 2025-03-25 @ 02:56am, id: 692741072 / R_kgDOKUpj0A