peilin-chen / Zhulong-RISCV-CPU

CPU Design Based on RISCV ISA

Date Created 2024-06-08 (5 months ago)
Commits 82 (last one 4 months ago)
Stargazers 74 (0 this week)
Watchers 3 (0 this week)
Forks 18
License mit
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RepositoryStats indexes 579,555 repositories, of these peilin-chen/Zhulong-RISCV-CPU is ranked #353,665 (39th percentile) for total stargazers, and #420,420 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #283/533.

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82 commits on the default branch (main) since jan '22

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updated: 2024-11-05 @ 07:44pm, id: 812224562 / R_kgDOMGmQMg