peilin-chen / Zhulong-RISCV-CPU

CPU Design Based on RISCV ISA

peilin-chen
peilin-chen
Date Created 2024-06-08 (9 months ago)
Commits 82 (last one 9 months ago)
Stargazers 95 (2 this week)
Watchers 4 (0 this week)
Forks 20
License mit
Ranking

RepositoryStats indexes 627,954 repositories, of these peilin-chen/Zhulong-RISCV-CPU is ranked #316,215 (50th percentile) for total stargazers, and #364,130 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #256/609.

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

82 commits on the default branch (main) since jan '22

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Yearly Commits

Commits to the default branch (main) per year

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Issue History

No issues have been posted

Languages

The primary language is Verilog but there's also others...

VerilogVerilogSchemeSchemeCCRoffRoffTclTclHCLHCLMakefileMakefileShellShellPythonPythonBatchfileBatchfileOtherOther

updated: 2025-03-14 @ 10:52pm, id: 812224562 / R_kgDOMGmQMg