Essenceia / low-latency-ethernet

RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.

Essenceia
Essenceia
Date Created 2023-07-16 (about a year ago)
Commits 172 (last one about a year ago)
Stargazers 35 (0 this week)
Watchers 4 (0 this week)
Forks 18
License mit
Ranking

RepositoryStats indexes 633,911 repositories, of these Essenceia/low-latency-ethernet is ranked #575,085 (9th percentile) for total stargazers, and #366,660 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #555/623.

Essenceia/low-latency-ethernet is also tagged with popular topics, for these it's ranked: fpga (#493/515),  tcp (#485/512),  verilog (#288/309)

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

4444443.53.533333310 Jan10 Jan20 Jan20 JanFeb '25Feb '2510 Feb10 Feb20 Feb20 FebMar '25Mar '2510 Mar10 Mar20 Mar20 MarApr '25Apr '25

Recent Commit History

172 commits on the default branch (master) since jan '22

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Yearly Commits

Commits to the default branch (master) per year

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Issue History

No issues have been posted

Languages

The primary language is Verilog but there's also others...

VerilogVerilogCCSystemVerilogSystemVerilogMakefileMakefileC++C++TclTcl

updated: 2025-03-26 @ 01:31pm, id: 666912088 / R_kgDOJ8BFWA