analogdevicesinc / hdl

HDL libraries and projects

Date Created 2014-02-20 (11 years ago)
Commits 6,936 (last one 6 hours ago)
Stargazers 1,585 (6 this week)
Watchers 159 (0 this week)
Forks 1,538
License other
Ranking

RepositoryStats indexes 616,861 repositories, of these analogdevicesinc/hdl is ranked #33,821 (95th percentile) for total stargazers, and #9,708 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #11/601.

analogdevicesinc/hdl is also tagged with popular topics, for these it's ranked: hacktoberfest (#1,870/15386),  fpga (#19/503),  verilog (#15/299)

Other Information

analogdevicesinc/hdl has 34 open pull requests on Github, 1,215 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 12 open issues and 78 closed issues.

There have been 16 releases, the latest one was published on 2024-11-21 (3 months ago) with the name 2023_r2.

Homepage URL: https://wiki.analog.com/resources/fpga/docs/hdl

Star History

Github stargazers over time

1.6k1.6k1.4k1.4k1.2k1.2k1k1k800800600600400400200200002015201520162016201720172018201820192019202020202021202120222022202320232024202420252025

Watcher History

Github watchers over time, collection started in '23

16216216016015815815615615415415215215015014814814614614414420232023Feb '23Feb '23Apr '23Apr '23Jun '23Jun '23Aug '23Aug '23Oct '23Oct '23Dec '23Dec '23Feb '24Feb '24Apr '24Apr '24Jun '24Jun '24Aug '24Aug '24Oct '24Oct '24Dec '24Dec '24Feb '25Feb '25

Recent Commit History

874 commits on the default branch (main) since jan '22

90090080080070070060060050050040040030030020020010010000Jul '22Jul '2220232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Yearly Commits

Commits to the default branch (main) per year

1.6k1.6k1.4k1.4k1.2k1.2k1k1k8008006006004004002002000020142014201520152016201620172017201820182019201920202020202120212022202220242024

Issue History

Total Issues
Open Issues
Closed Issues
909080807070606050504040303020201010002015201520162016201720172018201820192019202020202021202120222022202320232024202420252025

Languages

The primary language is Verilog but there's also others...

VerilogVerilogTclTclMakefileMakefileVHDLVHDLSystemVerilogSystemVerilogPerlPerlShellShellMATLABMATLABPythonPython

updated: 2025-02-19 @ 01:49pm, id: 17035121 / R_kgDOAQPvcQ