sudhamshu091 / 32-Verilog-Mini-Projects

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM

Date Created 2020-12-02 (4 years ago)
Commits 317 (last one 4 months ago)
Stargazers 644 (5 this week)
Watchers 9 (0 this week)
Forks 120
License other
Ranking

RepositoryStats indexes 628,836 repositories, of these sudhamshu091/32-Verilog-Mini-Projects is ranked #77,952 (88th percentile) for total stargazers, and #217,277 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #38/613.

sudhamshu091/32-Verilog-Mini-Projects is also tagged with popular topics, for these it's ranked: verilog (#43/306)

Other Information

sudhamshu091/32-Verilog-Mini-Projects has Github issues enabled, there is 1 open issue and 6 closed issues.

Star History

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

7 commits on the default branch (main) since jan '22

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Issue History

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Languages

The primary language is Verilog but there's also others...

VerilogVerilogPythonPythonCoqCoq

updated: 2025-03-19 @ 09:43pm, id: 317919042 / R_kgDOEvMPQg