AngeloJacobo / UberDDR3

Opensource DDR3 Controller

Date Created 2023-03-02 (about a year ago)

Commits 378 (last one 25 days ago)

Stargazers 212 (3 this week)

Watchers 10 (0 this week)

Forks 35

License gpl-3.0

Ranking

RepositoryStats indexes 584,353 repositories, of these AngeloJacobo/UberDDR3 is ranked #171,498 (71st percentile) for total stargazers, and #206,270 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #107/535.

AngeloJacobo/UberDDR3 is also tagged with popular topics, for these it's ranked: fpga (#142/478), verilog (#93/282)

Other Information

AngeloJacobo/UberDDR3 has Github issues enabled, there are 2 open issues and 6 closed issues.

All Topics

phy ddr3 fpga verilog ddr3-phy controller ddr3-controller memory-controller

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

378 commits on the default branch (main) since jan '22

Yearly Commits

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Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2024-11-20 @ 11:38am, id: 608616106 / R_kgDOJEa-qg