siriusm46 / Sources-for-FPGA-and-VLSI-Design

If you are interested in Digital Hardware Design and/or interested in chip and VLSI design, you may like this repo!

siriusm46
siriusm46
Date Created 2024-08-20 (7 months ago)
Commits 8 (last one 6 months ago)
Stargazers 32 (0 this week)
Watchers 2 (0 this week)
Forks 2
License unknown
Ranking

RepositoryStats indexes 630,459 repositories, of these siriusm46/Sources-for-FPGA-and-VLSI-Design is ranked #588,020 (7th percentile) for total stargazers, and #480,560 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #569/615.

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

8 commits on the default branch (main) since jan '22

887766554433221100Sep '24Sep '24Oct '24Oct '24Nov '24Nov '24Dec '24Dec '2420252025Feb '25Feb '25Mar '25Mar '25

Yearly Commits

Commits to the default branch (main) per year

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Issue History

No issues have been posted

Languages

The only known language in this repository is Verilog

VerilogVerilog

updated: 2025-03-09 @ 01:38am, id: 844874854 / R_kgDOMlvEZg