WangXuan95 / FPGA-UART

This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调试器。

WangXuan95
WangXuan95
Date Created 2019-08-01 (5 years ago)
Commits 16 (last one about a year ago)
Stargazers 175 (4 this week)
Watchers 2 (0 this week)
Forks 35
License gpl-3.0
Ranking

RepositoryStats indexes 632,768 repositories, of these WangXuan95/FPGA-UART is ranked #207,862 (67th percentile) for total stargazers, and #481,481 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #135/618.

WangXuan95/FPGA-UART is also tagged with popular topics, for these it's ranked: fpga (#174/515),  verilog (#110/308)

Other Information

Homepage URL: https://gitee.com/wangxuan95/FPGA-UART

All Topics
rtl fpga uart verilog

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

10 commits on the default branch (master) since jan '22

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Yearly Commits

Commits to the default branch (master) per year

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Issue History

No issues have been posted

Languages

The primary language is Verilog but there's also others...

VerilogVerilogBatchfileBatchfile

updated: 2025-03-28 @ 10:51am, id: 199992663 / R_kgDOC-ulVw