WangXuan95 / FPGA-UART

This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调试器。

WangXuan95
WangXuan95
Date Created 2019-08-01 (5 years ago)
Commits 16 (last one about a year ago)
Stargazers 120 (3 this week)
Watchers 3 (0 this week)
Forks 27
License gpl-3.0
Ranking

RepositoryStats indexes 589,134 repositories, of these WangXuan95/FPGA-UART is ranked #257,999 (56th percentile) for total stargazers, and #424,515 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #194/549.

WangXuan95/FPGA-UART is also tagged with popular topics, for these it's ranked: fpga (#217/482),  verilog (#136/284)

Other Information

Homepage URL: https://gitee.com/wangxuan95/FPGA-UART

All Topics
rtl fpga uart verilog

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

10 commits on the default branch (master) since jan '22

Yearly Commits

Commits to the default branch (master) per year

Issue History

No issues have been posted

Languages

The primary language is Verilog but there's also others...

updated: 2024-12-03 @ 10:06am, id: 199992663 / R_kgDOC-ulVw