renyangang / riscv-mcu

This project utilizes the Digital circuit simulation software,to build a CPU that supports a simple instruction set and simple peripheral circuit simulation. The goal is to support system boot, startup, operation, interrupt handling, peripheral control, and other functions.

renyangang
renyangang
Date Created 2024-08-20 (7 months ago)
Commits 85 (last one 3 months ago)
Stargazers 53 (2 this week)
Watchers 2 (0 this week)
Forks 11
License apache-2.0
Ranking

RepositoryStats indexes 632,768 repositories, of these renyangang/riscv-mcu is ranked #472,458 (25th percentile) for total stargazers, and #481,481 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #426/618.

Star History

Github stargazers over time

60605050404030302020101000Oct '24Oct '24Nov '24Nov '24Dec '24Dec '2420252025Feb '25Feb '25Mar '25Mar '25

Watcher History

Github watchers over time, collection started in '23

3333222222111115 Nov15 NovDec '24Dec '2415 Dec15 DecJan '25Jan '2515 Jan15 JanFeb '25Feb '2515 Feb15 FebMar '25Mar '2515 Mar15 Mar

Recent Commit History

85 commits on the default branch (master) since jan '22

90908080707060605050404030302020101000Sep '24Sep '24Oct '24Oct '24Nov '24Nov '24Dec '24Dec '2420252025Feb '25Feb '25Mar '25Mar '25

Yearly Commits

Commits to the default branch (master) per year

9090808070706060505040403030202010100020242024

Issue History

Total Issues
Open Issues
Closed Issues
1111110.50.5000000Oct '24Oct '24Nov '24Nov '24Dec '24Dec '2420252025Feb '25Feb '25Mar '25Mar '25

Languages

The primary language is Verilog but there's also others...

VerilogVerilogCCC++C++AssemblyAssemblyMakefileMakefilePythonPythonForthForthBatchfileBatchfile

updated: 2025-03-27 @ 09:03pm, id: 844918586 / R_kgDOMlxvOg