ultraembedded / core_jpeg

High throughput JPEG decoder in Verilog for FPGA

Date Created 2020-10-18 (4 years ago)

Commits 12 (last one 4 years ago)

Stargazers 212 (1 this week)

Watchers 10 (0 this week)

Forks 42

License apache-2.0

Ranking

RepositoryStats indexes 585,880 repositories, of these ultraembedded/core_jpeg is ranked #171,660 (71st percentile) for total stargazers, and #206,429 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #109/538.

ultraembedded/core_jpeg is also tagged with popular topics, for these it's ranked: fpga (#144/478), verilog (#95/282)

Other Information

ultraembedded/core_jpeg has 1 open pull request on Github, 0 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 6 open issues and 0 closed issues.

All Topics

fpga mjpeg verilog axi-stream motion-jpeg verilog-hdl jpeg-decoder

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0 commits on the default branch (main) since jan '22

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The primary language is Verilog but there's also others...

updated: 2024-11-20 @ 02:52pm, id: 305197324 / R_kgDOEjDxDA