RuSys / Verugent

Verilog generation tool written in Rust

Date Created 2018-07-26 (6 years ago)

Commits 51 (last one about a year ago)

Stargazers 57 (0 this week)

Watchers 6 (0 this week)

Forks 4

License apache-2.0

Ranking

RepositoryStats indexes 585,880 repositories, of these RuSys/Verugent is ranked #424,736 (28th percentile) for total stargazers, and #298,152 for total watchers. Github reports the primary language for this repository as Rust, for repositories using this language it is ranked #11,715/16,767.

RuSys/Verugent is also tagged with popular topics, for these it's ranked: rust (#5,533/7206)

Other Information

RuSys/Verugent has Github issues enabled, there is 1 open issue and 2 closed issues.

All Topics

rust verilog-hdl verilog-verugent

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

1 commits on the default branch (master) since jan '22

Yearly Commits

Commits to the default branch (master) per year

Issue History

Languages

The only known language in this repository is Rust

updated: 2024-11-15 @ 09:58pm, id: 142471289 / R_kgDOCH3weQ