jfoshea / Viterbi-Decoder-in-Verilog

An efficient implementation of the Viterbi decoding algorithm in Verilog

Date Created 2018-03-16 (7 years ago)

Commits 25 (last one 6 years ago)

Stargazers 51 (0 this week)

Watchers 3 (0 this week)

Forks 23

License unknown

Ranking

RepositoryStats indexes 634,026 repositories, of these jfoshea/Viterbi-Decoder-in-Verilog is ranked #485,164 (23rd percentile) for total stargazers, and #418,530 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #443/623.

jfoshea/Viterbi-Decoder-in-Verilog is also tagged with popular topics, for these it's ranked: fpga (#428/515)

Other Information

jfoshea/Viterbi-Decoder-in-Verilog has 1 open pull request on Github, 0 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there is 1 open issue and 0 closed issues.

All Topics

fpga xilinx verilog-hdl viterbi-decoder viterbi-algorithm

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The primary language is Verilog but there's also others...

updated: 2025-03-07 @ 12:30am, id: 125450996 / R_kgDOB3o69A