PyHDI / Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

Date Created 2013-12-02 (11 years ago)

Commits 364 (last one about a year ago)

Stargazers 647 (1 this week)

Watchers 45 (0 this week)

Forks 182

License apache-2.0

Ranking

RepositoryStats indexes 595,856 repositories, of these PyHDI/Pyverilog is ranked #75,231 (87th percentile) for total stargazers, and #47,053 for total watchers. Github reports the primary language for this repository as Python, for repositories using this language it is ranked #12,074/119,431.

PyHDI/Pyverilog is also tagged with popular topics, for these it's ranked: python (#3,979/22324), parser (#188/1208), compiler (#262/1063), hardware (#73/451), code-generator (#42/166)

Other Information

PyHDI/Pyverilog has 6 open pull requests on Github, 26 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 70 open issues and 24 closed issues.

There have been 26 releases, the latest one was published on 2020-12-30 (3 years ago) with the name 1.3.0.

All Topics

parser python compiler hardware verilog-hdl code-generator dataflow-analyzer control-flow-analyzer

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Github watchers over time, collection started in '23

Recent Commit History

5 commits on the default branch (develop) since jan '22

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Languages

The primary language is Python but there's also others...

updated: 2024-12-21 @ 01:03pm, id: 14871471 / R_kgDOAOLrrw