chipsalliance / sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

Date Created 2019-08-08 (5 years ago)

Commits 8,782 (last one 16 hours ago)

Stargazers 297 (0 this week)

Watchers 19 (0 this week)

Forks 75

License isc

Ranking

RepositoryStats indexes 584,353 repositories, of these chipsalliance/sv-tests is ranked #134,047 (77th percentile) for total stargazers, and #116,307 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #29/173.

chipsalliance/sv-tests is also tagged with popular topics, for these it's ranked: verilog (#74/282)

Other Information

chipsalliance/sv-tests has 21 open pull requests on Github, 4,207 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 45 open issues and 234 closed issues.

Homepage URL: https://chipsalliance.github.io/sv-tests-results/

All Topics

hdl rtl verilog symbiflow systemverilog compliance-testing

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5,872 commits on the default branch (master) since jan '22

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The primary language is SystemVerilog but there's also others...

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updated: 2024-11-21 @ 02:31am, id: 201299456 / R_kgDOC_-WAA