furrtek / SiliconRE

Traces, schematics, and general infos about custom chips reverse-engineered from silicon

Date Created 2019-12-27 (5 years ago)
Commits 198 (last one 23 hours ago)
Stargazers 169 (0 this week)
Watchers 20 (0 this week)
Forks 14
License gpl-2.0
Ranking

RepositoryStats indexes 616,225 repositories, of these furrtek/SiliconRE is ranked #208,797 (66th percentile) for total stargazers, and #111,845 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #136/600.

furrtek/SiliconRE is also tagged with popular topics, for these it's ranked: reverse-engineering (#582/1265),  fpga (#172/503),  verilog (#110/299)

Other Information

furrtek/SiliconRE has 1 open pull request on Github, 4 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 18 open issues and 3 closed issues.

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

202019.519.5191918.518.5181817.517.5171716.516.5161620232023Feb '23Feb '23Apr '23Apr '23Jun '23Jun '23Aug '23Aug '23Oct '23Oct '23Dec '23Dec '23Feb '24Feb '24Apr '24Apr '24Jun '24Jun '24Aug '24Aug '24Oct '24Oct '24Dec '24Dec '24Feb '25Feb '25

Recent Commit History

88 commits on the default branch (master) since jan '22

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Yearly Commits

Commits to the default branch (master) per year

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Issue History

Total Issues
Open Issues
Closed Issues
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Languages

The primary language is Verilog but there's also others...

VerilogVerilogPythonPythonBatchfileBatchfile

updated: 2025-02-18 @ 05:22am, id: 230430812 / R_kgDODbwYXA