furrtek / SiliconRE

Traces, schematics, and general infos about custom chips reverse-engineered from silicon

Date Created 2019-12-27 (5 years ago)

Commits 205 (last one 5 days ago)

Stargazers 174 (2 this week)

Watchers 19 (0 this week)

Forks 14

License gpl-2.0

Ranking

RepositoryStats indexes 633,559 repositories, of these furrtek/SiliconRE is ranked #208,143 (67th percentile) for total stargazers, and #114,322 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #136/623.

furrtek/SiliconRE is also tagged with popular topics, for these it's ranked: reverse-engineering (#592/1297), fpga (#175/515), verilog (#111/309)

Other Information

furrtek/SiliconRE has 1 open pull request on Github, 4 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 18 open issues and 3 closed issues.

All Topics

hdl asic chip cpld fpga decap repro taito arcade konami silicon verilog gate-array video-game arcade-game standard-cell reverse-engineering

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

95 commits on the default branch (master) since jan '22

Yearly Commits

Commits to the default branch (master) per year

Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2025-03-28 @ 12:41am, id: 230430812 / R_kgDODbwYXA