Trending repositories for topic fpga

John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs

Digital logic design tool and simulator

State-of-the-art native debugging tools

SERV - The SErial RISC-V CPU

Package manager and build abstraction tool for FPGA/ASIC development

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

The last Pcileech DMA CFW guide you will ever need. Sponsored by DMAPolice.com

This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调试器。

Bus bridges and other odds and ends

Modular hardware build system

32-bit Superscalar RISC-V CPU

A modern hardware definition language and toolchain based on Python

Scala based HDL

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Curso de Lógica Digital

This is xc7z020clg400 FPGA hardware core board design

"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.

A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

Curso de Lógica Digital

This is xc7z020clg400 FPGA hardware core board design

"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

The last Pcileech DMA CFW guide you will ever need. Sponsored by DMAPolice.com

Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.

A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调试器。

Learn how to build our own RV32I core and use it on FPGA.

The ultimate Amiga games & demo scene setup for MiSTer & Pocket FPGAs, emulators, and real hardware. Open source, community driven. This is an Amiga HDF image builder that uses WHDLoad and custom inst...

Convolutional accelerator kernel, target ASIC & FPGA

A股订单簿工具，使用逐笔行情进行订单簿重建、千档快照发布、各档委托队列展示等，包括python模型和FPGA HLS实现。

FPGA cores compatible with multiple arcade game machines and KiCAD schematics of arcade games. Working on MiSTer FPGA/Analogue Pocket

Bus bridges and other odds and ends

xkISP：Xinkai ISP IP Core (HLS)

SERV - The SErial RISC-V CPU

The complete codebase for Frame

Code generation tool for control and status registers

Installs Vivado on M1/M2/M3 macs

Package manager and build abstraction tool for FPGA/ASIC development

A huge collection of VHDL/Verilog open-source IP cores scraped from the web

John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs

Digital logic design tool and simulator

SERV - The SErial RISC-V CPU

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

State-of-the-art native debugging tools

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Build your hardware, easily!

A FPGA friendly 32 bit RISC-V CPU implementation

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

The last Pcileech DMA CFW guide you will ever need. Sponsored by DMAPolice.com

Package manager and build abstraction tool for FPGA/ASIC development

PaddlePaddle High Performance Deep Learning Inference Engine for Mobile and Edge (飞桨高性能深度学习端侧推理引擎）

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调试器。

A股订单簿工具，使用逐笔行情进行订单簿重建、千档快照发布、各档委托队列展示等，包括python模型和FPGA HLS实现。

32-bit Superscalar RISC-V CPU

A modern hardware definition language and toolchain based on Python

IC implementation of Systolic Array for TPU

Package manager and build tool for VHDL/SystemVerilog

Curso de Lógica Digital

A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

基于 pcileech-fpga 的自定义/修改 DMA固件创建的详细说明

This is xc7z020clg400 FPGA hardware core board design

Dual-Mode PSK Transceiver on SDR With FPGA

The last Pcileech DMA CFW guide you will ever need. Sponsored by DMAPolice.com

"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调试器。

NOVA34 is an open-source, ultra-small 34mm Linux & Android board with custom PCB design, optimized for embedded systems and peripherals integration.

Learn how to build our own RV32I core and use it on FPGA.

Re-coded Xilinx primitives for Verilator use

Open source ISS and logic RISC-V 32 bit project

The ultimate Amiga games & demo scene setup for MiSTer & Pocket FPGAs, emulators, and real hardware. Open source, community driven. This is an Amiga HDF image builder that uses WHDLoad and custom inst...

This repository contains all the necessary material to implement a YOLOv3 object detection algorithm on the PYNQ-Z2 FPGA. There is a step-by-step tutorial associated so everyone can do it.

A股订单簿工具，使用逐笔行情进行订单簿重建、千档快照发布、各档委托队列展示等，包括python模型和FPGA HLS实现。

The SpinalHDL design of the Proteus core, an extensible RISC-V core.

IC implementation of Systolic Array for TPU

The complete codebase for Frame

SERV - The SErial RISC-V CPU

John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs

Digital logic design tool and simulator

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

A股订单簿工具，使用逐笔行情进行订单簿重建、千档快照发布、各档委托队列展示等，包括python模型和FPGA HLS实现。

Build your hardware, easily!

State-of-the-art native debugging tools

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

Machine learning on FPGAs using HLS

SERV - The SErial RISC-V CPU

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

The last Pcileech DMA CFW guide you will ever need. Sponsored by DMAPolice.com

NOVA34 is an open-source, ultra-small 34mm Linux & Android board with custom PCB design, optimized for embedded systems and peripherals integration.

A FPGA friendly 32 bit RISC-V CPU implementation

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Modular hardware build system

Opensource DDR3 Controller

The Ultra-Low Power RISC-V Core

:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

32-bit Superscalar RISC-V CPU

基于 pcileech-fpga 的自定义/修改 DMA固件创建的详细说明

NOVA34 is an open-source, ultra-small 34mm Linux & Android board with custom PCB design, optimized for embedded systems and peripherals integration.

基于 pcileech-fpga 的自定义/修改 DMA固件创建的详细说明

A股订单簿工具，使用逐笔行情进行订单簿重建、千档快照发布、各档委托队列展示等，包括python模型和FPGA HLS实现。

Curso de Lógica Digital

Package manager and build tool for VHDL/SystemVerilog

The last Pcileech DMA CFW guide you will ever need. Sponsored by DMAPolice.com

This is xc7z020clg400 FPGA hardware core board design

Learn how to build our own RV32I core and use it on FPGA.

This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调试器。

Next Generation IDE for Electronics Development

RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.

High Granularity Quantizarion for Ultra-Fast Machine Learning Applications on FPGAs

IC implementation of Systolic Array for TPU

No description

Opensource DDR3 Controller

This repository contains all the necessary material to implement a YOLOv3 object detection algorithm on the PYNQ-Z2 FPGA. There is a step-by-step tutorial associated so everyone can do it.

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPG...

"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

A Python library for converting images into FPGA-displayable pixel art.

The last Pcileech DMA CFW guide you will ever need. Sponsored by DMAPolice.com

Verilog package manager written in Rust

Learn how to build our own RV32I core and use it on FPGA.

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...

An High-Performance SLAM Hardware Accelerator Implementation for FPGA

基于 pcileech-fpga 的自定义/修改 DMA固件创建的详细说明

riffpga -- write FPGA bitstreams through a USB drive, get USB serial and dynamic clocking in a platform independent way

Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples => https://www.chili-chips.xyz/open-cologne | Also see https://na...

An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器

building blocks for accelerating ZK proofs over binary fields

NOVA34 is an open-source, ultra-small 34mm Linux & Android board with custom PCB design, optimized for embedded systems and peripherals integration.

Microcontroller firmware for retro FPGA support MCUs

NTUEE Digital Circuit Lab 24Fall

A tool for compression of lookup tables and generation of their hardware files in Verilog for RTL designs

The open-source Zynq 7000 BSP generator for openXC7

John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs

Digital logic design tool and simulator

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

State-of-the-art native debugging tools

Build your hardware, easily!

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

A FPGA friendly 32 bit RISC-V CPU implementation

Open source FPGA-based NIC and platform for in-network compute

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

A Python library for converting images into FPGA-displayable pixel art.

The Ultra-Low Power RISC-V Core

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Machine learning on FPGAs using HLS

RISC-V CPU Core (RV32IM)

RISC-V Linux SoC, marchID: 0x2b

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Must-have verilog systemverilog modules

:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

SERV - The SErial RISC-V CPU

Vitis In-Depth Tutorials

A Python library for converting images into FPGA-displayable pixel art.

A 3D FPGA GPU for real-time rasterization with a tile-based deferred rendering (TBDR) architecture, featuring transform & lighting (T&L), back-face culling, MSAA anti-aliasing, ordered dithering, etc.

Learn how to build our own RV32I core and use it on FPGA.

End-to-end synthesis and P&R toolchain

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...

An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器

An FPGA reverse engineering and documentation project

My own FPGA architecture simulated in VHDL, realized with 7400-logic on PCB.

NOVA34 is an open-source, ultra-small 34mm Linux & Android board with custom PCB design, optimized for embedded systems and peripherals integration.

Verilog implementation of PAL, NTSC and SECAM color encoding

riffpga -- write FPGA bitstreams through a USB drive, get USB serial and dynamic clocking in a platform independent way

High Granularity Quantizarion for Ultra-Fast Machine Learning Applications on FPGAs

The complete codebase for Frame

Curso de Lógica Digital

Opensource DDR3 Controller

Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

Tutorial of a HW design of MicroBlaze using DDR3 RAM on Arty A7 board; DDR3 RAM speed test application

A FPGA-based receiver for Behringers Ultranet (X32, P16-I, P16-M, etc.)

This is xc7z020clg400 FPGA hardware core board design

building blocks for accelerating ZK proofs over binary fields