Trending repositories for topic fpga
John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product ...
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-speed...
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
Theory of digital signal processing (DSP): signals, filtration (IIR, FIR, CIC, MAF), transforms (FFT, DFT, Hilbert, Z-transform) etc.
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product ...
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
Allo: A Programming Model for Composable Accelerator Design
An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-speed...
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC,包含一个RV32I CPU、一个简单可扩展的总线、一些外设。
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
Theory of digital signal processing (DSP): signals, filtration (IIR, FIR, CIC, MAF), transforms (FFT, DFT, Hilbert, Z-transform) etc.
Structural Netlist API (and more) for EDA post synthesis flow development
Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images
A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
IC implementation of Systolic Array for TPU
Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器,用来读写硬盘。
:atm: Second life for FPGA boards which can be repurposed to DYI/Hobby projects ...............................................................................................
John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-speed...
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Verilog implementation of PAL, NTSC and SECAM color encoding
Tutorial of a HW design of MicroBlaze using DDR3 RAM on Arty A7 board; DDR3 RAM speed test application
Allo: A Programming Model for Composable Accelerator Design
A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPG...
My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
Network Development Kit (NDK) for FPGA cards with example application
High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.
A configurable and approachable tool for FPGA debugging and rapid prototyping.
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...
This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块:UART接收器、UART发送器、UART转AXI4交互式调试器。
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples => https://www.chili-chips.xyz/open-cologne | Also see https://na...
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...
John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
A Python library for converting images into FPGA-displayable pixel art.
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
A Python library for converting images into FPGA-displayable pixel art.
A 3D FPGA GPU for real-time rasterization with a tile-based deferred rendering (TBDR) architecture, featuring transform & lighting (T&L), back-face culling, MSAA anti-aliasing, ordered dithering, etc.
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
Allo: A Programming Model for Composable Accelerator Design
A configurable and approachable tool for FPGA debugging and rapid prototyping.
Commodore C64 core for the Tang Nano 20K Primer 25K Mega 60k and Mega 138K Pro FPGA
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
A FPGA-based receiver for Behringers Ultranet (X32, P16-I, P16-M, etc.)
Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
A textbook on understanding system on chip design
RISC-V Embedded Processor for Approximate Computing
building blocks for accelerating ZK proofs over binary fields
Методические материалы по разработке процессора архитектуры RISC-V