Trending repositories for topic fpga
A Python library for converting images into FPGA-displayable pixel art.
John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference
IC implementation of Systolic Array for TPU
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
A modern hardware definition language and toolchain based on Python
A Python library for converting images into FPGA-displayable pixel art.
FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference
IC implementation of Systolic Array for TPU
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA
Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedded programs targeted at the microprocessor to control the perip...
An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。
FPGA-based USB fast data transmission using FT232H/FT600 chip. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
A Python library for converting images into FPGA-displayable pixel art.
John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference
An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
A Python library for converting images into FPGA-displayable pixel art.
FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference
A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA
I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has ...
An example of simulating Verilog / FPGA gateware inside a VCV Rack plugin.
IC implementation of Systolic Array for TPU
Commodore C64 core for the Tang Nano 20K, Primer 25K and Mega 138K FPGA
3 modules: UART receiver, UART transmitter, UART to AXI4 master. 3个模块：UART接收器、UART发送器、UART转AXI4交互式调试器
An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。
Structural Netlist API (and more) for EDA post synthesis flow development
QONNX: Arbitrary-Precision Quantized Neural Networks in ONNX
John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs
A Python library for converting images into FPGA-displayable pixel art.
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
A configurable and approachable tool for FPGA debugging and rapid prototyping.
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
A Python library for converting images into FPGA-displayable pixel art.
A configurable and approachable tool for FPGA debugging and rapid prototyping.
FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference
Commodore C64 core for the Tang Nano 20K, Primer 25K and Mega 138K FPGA
A FPGA-based receiver for Behringers Ultranet (X32, P16-I, P16-M, etc.)
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA
Research and Materials on Hardware implementation of Transformer Model
🔥🔥🔥 A collection of some awesome public NVIDIA CUDA, cuBLAS, cuDNN, TensorRT, AMD ROCm and FPGA projects.
IC implementation of Systolic Array for TPU
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
Autonomous pre-boot DMA attack hardware implant for M.2 slot based on PicoEVB development board
Commodore C64 core for the Tang Nano 20K, Primer 25K and Mega 138K FPGA
A FPGA-based receiver for Behringers Ultranet (X32, P16-I, P16-M, etc.)
John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器...
PaddlePaddle High Performance Deep Learning Inference Engine for Mobile and Edge (飞桨高性能深度学习端侧推理引擎）
A modern hardware definition language and toolchain based on Python
:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
A configurable and approachable tool for FPGA debugging and rapid prototyping.
🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit
A Python library for converting images into FPGA-displayable pixel art.
🔥🔥🔥 A collection of some awesome public NVIDIA CUDA, cuBLAS, cuDNN, TensorRT, AMD ROCm and FPGA projects.
Autonomous pre-boot DMA attack hardware implant for M.2 slot based on PicoEVB development board
Research and Materials on Hardware implementation of Transformer Model
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.
Ensō is a high-performance streaming interface for NIC-application communication.
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference
Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核