Trending repositories for topic fpga

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

Digital logic design tool and simulator

John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs

Build your hardware, easily!

The last Pcileech DMA CFW guide you will ever need.

Must-have verilog systemverilog modules

A modern hardware definition language and toolchain based on Python

Samples for Intel® oneAPI Toolkits

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

Machine learning on FPGAs using HLS

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

State-of-the-art native debugging tools

RISC-V Linux SoC, marchID: 0x2b

Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

Vitis In-Depth Tutorials

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

PCI Express DIY hacking toolkit for Xilinx SP605. This repository is also home of Hyper-V Backdoor and Boot Backdoor, check readme for links and info

Send video/audio over HDMI on an FPGA

The last Pcileech DMA CFW guide you will ever need.

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

A series of CORDIC related projects

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

Samples for Intel® oneAPI Toolkits

SD-Card controller, using either SPI, SDIO, or eMMC interfaces

High throughput JPEG decoder in Verilog for FPGA

Opensource DDR3 Controller

A configurable C++ generator of pipelined Verilog FFT cores

RISC-V Linux SoC, marchID: 0x2b

Machine learning on FPGAs using HLS

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product ...

Must-have verilog systemverilog modules

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

32-bit RISC-V system on chip for iCE40 FPGAs

Tutorial notebooks for hls4ml

A modern hardware definition language and toolchain based on Python

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs

Digital logic design tool and simulator

The last Pcileech DMA CFW guide you will ever need.

Build your hardware, easily!

RISC-V CPU Core (RV32IM)

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

State-of-the-art native debugging tools

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Machine learning on FPGAs using HLS

Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

Samples for Intel® oneAPI Toolkits

A modern hardware definition language and toolchain based on Python

Vitis In-Depth Tutorials

The Ultra-Low Power RISC-V Core

Must-have verilog systemverilog modules

RISC-V Linux SoC, marchID: 0x2b

Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

Opensource DDR3 Controller

The last Pcileech DMA CFW guide you will ever need.

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design

Library of approximate arithmetic circuits

Package manager and build tool for HDLs

An open-source HDL register code generator fast enough to run in real time.

Opensource DDR3 Controller

Introduction to FPGA emulation and digital design. This capstone project was part of the 2021 University of San Diego Shiley-Marcos School of Engineering & Computing Showcase.

This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G ...

Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples. https://www.chili-chips.xyz/open-cologne

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

For aspiring hardware engineers out there.

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database

A new Hardware Design Language that keeps you in the driver's seat

A股订单簿工具，使用逐笔行情进行订单簿重建、千档快照发布、各档委托队列展示等，包括python模型和FPGA HLS实现。

Maia SDR is an open-source FPGA-based SDR project focusing on the ADALM Pluto

Convolutional accelerator kernel, target ASIC & FPGA

A series of CORDIC related projects

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs

Digital logic design tool and simulator

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

Build your hardware, easily!

Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

The last Pcileech DMA CFW guide you will ever need.

A Python library for converting images into FPGA-displayable pixel art.

A FPGA friendly 32 bit RISC-V CPU implementation

State-of-the-art native debugging tools

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

Open source FPGA-based NIC and platform for in-network compute

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Machine learning on FPGAs using HLS

The Ultra-Low Power RISC-V Core

RISC-V CPU Core (RV32IM)

Brevitas: neural network quantization in PyTorch

SERV - The SErial RISC-V CPU

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

Must-have verilog systemverilog modules

The last Pcileech DMA CFW guide you will ever need.

Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...

An open-source HDL register code generator fast enough to run in real time.

This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design

An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器

Open source ISS and logic RISC-V 32 bit project

Allo: A Programming Model for Composable Accelerator Design

A股订单簿工具，使用逐笔行情进行订单簿重建、千档快照发布、各档委托队列展示等，包括python模型和FPGA HLS实现。

Scale-able EDA for FPGA, Verilog/Vivado/Quartus and more

Control and status register code generator toolchain

一个开源的FPGA神经网络加速器。

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

Opensource DDR3 Controller

For aspiring hardware engineers out there.

A Python library for converting images into FPGA-displayable pixel art.

A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPG...

The complete codebase for Frame

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

Verilog package manager written in Rust

A Python library for converting images into FPGA-displayable pixel art.

An exquisite superscalar RV32GC processor.

Verilog package manager written in Rust

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

The last Pcileech DMA CFW guide you will ever need.

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

2023集创赛紫光同创杯一等奖项目

An High-Performance SLAM Hardware Accelerator Implementation for FPGA

Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples. https://www.chili-chips.xyz/open-cologne

Apple II FPGA Co-Processor

building blocks for accelerating ZK proofs over binary fields

An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器

An open-source HDL register code generator fast enough to run in real time.

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...

This repository contains all the necessary material to implement a YOLOv3 object detection algorithm on the PYNQ-Z2 FPGA. There is a step-by-step tutorial associated so everyone can do it.

RiscV based SOC with 2D and 3D graphics acceleration for Tang Nano 20K

A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPG...

John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

Digital logic design tool and simulator

State-of-the-art native debugging tools

Build your hardware, easily!

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

A Python library for converting images into FPGA-displayable pixel art.

A FPGA friendly 32 bit RISC-V CPU implementation

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Open source FPGA-based NIC and platform for in-network compute

Must-have verilog systemverilog modules

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

The Ultra-Low Power RISC-V Core

Universal utility for programming FPGA

RISC-V Linux SoC, marchID: 0x2b

An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器...

Machine learning on FPGAs using HLS

SERV - The SErial RISC-V CPU

Vitis In-Depth Tutorials

A Python library for converting images into FPGA-displayable pixel art.

A 3D FPGA GPU for real-time rasterization with a tile-based deferred rendering (TBDR) architecture, featuring transform & lighting (T&L), back-face culling, MSAA anti-aliasing, ordered dithering, etc.

Commodore C64 core for the Tang Nano 20K Primer 25K Mega 60k and Mega 138K Pro FPGA

A configurable and approachable tool for FPGA debugging and rapid prototyping.

An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器

A FPGA-based receiver for Behringers Ultranet (X32, P16-I, P16-M, etc.)

OpenGL 1.x implementation for FPGAs

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

HyperDbg's logic analyzer and chip-level hardware debugger

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...

Методические материалы по разработке процессора архитектуры RISC-V

Opensource DDR3 Controller

RISC-V Embedded Processor for Approximate Computing

Atari STE MiSTery core for the Tang Nano 20k FPGA

A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA

building blocks for accelerating ZK proofs over binary fields

This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design

"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

A VHDL IP for ECC (Elliptic Curve Cryptography) hardware acceleration

A new Hardware Design Language that keeps you in the driver's seat