wyvernSemi / riscV

Open source ISS and logic RISC-V 32 bit project

Date Created 2021-07-20 (3 years ago)

Commits 192 (last one 2 days ago)

Stargazers 40 (0 this week)

Watchers 8 (0 this week)

Forks 13

License gpl-3.0

Ranking

RepositoryStats indexes 584,353 repositories, of these wyvernSemi/riscV is ranked #512,804 (12th percentile) for total stargazers, and #244,799 for total watchers. Github reports the primary language for this repository as C++, for repositories using this language it is ranked #28,056/31,270.

wyvernSemi/riscV is also tagged with popular topics, for these it's ranked: linux (#5,386/5866), c-plus-plus (#1,358/1371), fpga (#445/478), verilog (#264/282), risc-v (#236/263), embedded-systems (#184/205)

All Topics

iss fpga linux 32-bit risc-v verilog cpu-model processor soft-core c-plus-plus co-simulation risc-processor embedded-systems

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

79 commits on the default branch (main) since jan '22

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Issue History

Languages

The primary language is C++ but there's also others...

updated: 2024-11-19 @ 07:51am, id: 387694296 / R_kgDOFxu-2A