wyvernSemi / riscV

Open source ISS and logic RISC-V 32 bit project

Date Created 2021-07-20 (3 years ago)

Commits 195 (last one 24 days ago)

Stargazers 40 (0 this week)

Watchers 8 (0 this week)

Forks 14

License gpl-3.0

Ranking

RepositoryStats indexes 595,856 repositories, of these wyvernSemi/riscV is ranked #520,769 (13th percentile) for total stargazers, and #246,776 for total watchers. Github reports the primary language for this repository as C++, for repositories using this language it is ranked #28,538/31,836.

wyvernSemi/riscV is also tagged with popular topics, for these it's ranked: linux (#5,463/5945), c-plus-plus (#1,358/1372), fpga (#448/488), verilog (#265/289), risc-v (#236/268), embedded-systems (#187/207)

All Topics

iss fpga linux 32-bit risc-v verilog cpu-model processor soft-core c-plus-plus co-simulation risc-processor embedded-systems

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

82 commits on the default branch (main) since jan '22

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Issue History

Languages

The primary language is C++ but there's also others...

updated: 2024-12-15 @ 04:35am, id: 387694296 / R_kgDOFxu-2A