wyvernSemi / riscV

Open source ISS and logic RISC-V 32 bit project

Date Created 2021-07-20 (3 years ago)
Commits 195 (last one 2 months ago)
Stargazers 42 (0 this week)
Watchers 8 (0 this week)
Forks 14
License gpl-3.0
Ranking

RepositoryStats indexes 616,861 repositories, of these wyvernSemi/riscV is ranked #524,416 (15th percentile) for total stargazers, and #248,889 for total watchers. Github reports the primary language for this repository as C++, for repositories using this language it is ranked #28,816/32,971.

wyvernSemi/riscV is also tagged with popular topics, for these it's ranked: linux (#5,502/6109),  c-plus-plus (#1,366/1385),  fpga (#454/503),  verilog (#273/299),  risc-v (#238/271),  embedded-systems (#193/213)

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

82 commits on the default branch (main) since jan '22

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Yearly Commits

Commits to the default branch (main) per year

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Issue History

Total Issues
Open Issues
Closed Issues
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Languages

The primary language is C++ but there's also others...

C++C++VerilogVerilogCCStataStataHTMLHTMLTclTclAssemblyAssemblyMakefileMakefilePythonPythonOtherOtherShellShell

updated: 2025-02-06 @ 06:03pm, id: 387694296 / R_kgDOFxu-2A