shawntsai0312 / NTUEE_DIGITAL_CIRCUIT_LAB_24FALL

NTUEE Digital Circuit Lab 24Fall

shawntsai0312
shawntsai0312
Date Created 2024-09-11 (6 months ago)
Commits 152 (last one 2 months ago)
Stargazers 35 (0 this week)
Watchers 1 (0 this week)
Forks 3
License unknown
Ranking

RepositoryStats indexes 628,089 repositories, of these shawntsai0312/NTUEE_DIGITAL_CIRCUIT_LAB_24FALL is ranked #570,389 (9th percentile) for total stargazers, and #554,057 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #177/193.

shawntsai0312/NTUEE_DIGITAL_CIRCUIT_LAB_24FALL is also tagged with popular topics, for these it's ranked: fpga (#490/509),  verilog (#287/305)

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

152 commits on the default branch (main) since jan '22

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Yearly Commits

Commits to the default branch (main) per year

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Issue History

No issues have been posted

Languages

The primary language is SystemVerilog but there's also others...

SystemVerilogSystemVerilogVerilogVerilogHTMLHTMLPythonPythonShellShellVHDLVHDLTclTclC++C++MakefileMakefile

updated: 2025-03-12 @ 07:59pm, id: 855615497 / R_kgDOMv-oCQ