shawntsai0312 / NTUEE_DIGITAL_CIRCUIT_LAB_24FALL

NTUEE Digital Circuit Lab 24Fall

Date Created 2024-09-11 (6 months ago)
Commits 152 (last one 2 months ago)
Stargazers 35 (0 this week)
Watchers 1 (0 this week)
Forks 3
License unknown
Ranking

RepositoryStats indexes 628,047 repositories, of these shawntsai0312/NTUEE_DIGITAL_CIRCUIT_LAB_24FALL is ranked #570,124 (9th percentile) for total stargazers, and #553,667 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #177/193.

shawntsai0312/NTUEE_DIGITAL_CIRCUIT_LAB_24FALL is also tagged with popular topics, for these it's ranked: fpga (#489/508),  verilog (#287/305)

Star History

Github stargazers over time

3535303025252020151510105500Jan '25Jan '2510 Jan10 Jan20 Jan20 JanFeb '25Feb '2510 Feb10 Feb20 Feb20 FebMar '25Mar '2510 Mar10 Mar

Watcher History

Github watchers over time, collection started in '23

2222111111000010 Jan10 Jan20 Jan20 JanFeb '25Feb '2510 Feb10 Feb20 Feb20 FebMar '25Mar '2510 Mar10 Mar

Recent Commit History

152 commits on the default branch (main) since jan '22

160160140140120120100100808060604040202000Oct '24Oct '24Nov '24Nov '24Dec '24Dec '2420252025Feb '25Feb '25Mar '25Mar '25

Yearly Commits

Commits to the default branch (main) per year

16016014014012012010010080806060404020200020242024

Issue History

No issues have been posted

Languages

The primary language is SystemVerilog but there's also others...

SystemVerilogSystemVerilogVerilogVerilogHTMLHTMLPythonPythonShellShellVHDLVHDLTclTclC++C++MakefileMakefile

updated: 2025-03-12 @ 07:59pm, id: 855615497 / R_kgDOMv-oCQ