iammituraj / pequeno_riscv

Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

Date Created 2023-12-08 (about a year ago)

Commits 39 (last one 22 days ago)

Stargazers 56 (0 this week)

Watchers 4 (0 this week)

Forks 5

License other

Ranking

RepositoryStats indexes 595,890 repositories, of these iammituraj/pequeno_riscv is ranked #435,221 (27th percentile) for total stargazers, and #377,353 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #127/178.

iammituraj/pequeno_riscv is also tagged with popular topics, for these it's ranked: fpga (#380/488), cpu (#245/285), risc-v (#197/268)

Other Information

There have been 2 releases, the latest one was published on 2024-10-04 (2 months ago) with the name v1.0_final.

Homepage URL: https://chipmunklogic.com

All Topics

cpu rtl fpga risc-v systemverilog

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Recent Commit History

39 commits on the default branch (main) since jan '22

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Languages

The primary language is SystemVerilog but there's also others...

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updated: 2024-12-04 @ 01:39am, id: 729319584 / R_kgDOK3iIoA