iammituraj / pequeno_riscv

Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.

Date Created 2023-12-08 (11 months ago)

Commits 38 (last one 18 days ago)

Stargazers 53 (0 this week)

Watchers 4 (0 this week)

Forks 5

License other

Ranking

RepositoryStats indexes 584,353 repositories, of these iammituraj/pequeno_riscv is ranked #445,226 (24th percentile) for total stargazers, and #373,290 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #129/173.

iammituraj/pequeno_riscv is also tagged with popular topics, for these it's ranked: fpga (#386/478), cpu (#250/284), risc-v (#200/263)

Other Information

There have been 2 releases, the latest one was published on 2024-10-04 (about a month ago) with the name v1.0_final.

Homepage URL: https://chipmunklogic.com

All Topics

cpu rtl fpga risc-v systemverilog

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Recent Commit History

38 commits on the default branch (main) since jan '22

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Languages

The primary language is SystemVerilog but there's also others...

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updated: 2024-11-19 @ 04:37am, id: 729319584 / R_kgDOK3iIoA