WangXuan95 / FPGA-RMII-SMII

An FPGA-based MII to RMII & SMII converter to connect 100M ethernet PHY chip such as LAN8720 or KSZ8041TLI-S. 基于FPGA的MII转RMII和MII转SMII，用来连接LAN8720、KSZ8041TLI-S等百兆以太网PHY芯片。

WangXuan95
WangXuan95
Date Created 2021-01-13 (3 years ago)
Commits 10 (last one about a year ago)
Stargazers 80 (0 this week)
Watchers 6 (0 this week)
Forks 17
License gpl-3.0
Ranking

RepositoryStats indexes 595,856 repositories, of these WangXuan95/FPGA-RMII-SMII is ranked #342,270 (43rd percentile) for total stargazers, and #300,666 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #272/563.

WangXuan95/FPGA-RMII-SMII is also tagged with popular topics, for these it's ranked: fpga (#301/488),  verilog (#186/289)

Other Information

WangXuan95/FPGA-RMII-SMII has Github issues enabled, there is 1 open issue and 1 closed issue.

Homepage URL: https://gitee.com/wangxuan95/FPGA-RMII-SMII

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8 commits on the default branch (main) since jan '22

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The primary language is Verilog but there's also others...

updated: 2024-12-18 @ 11:55pm, id: 329188560 / R_kgDOE58E0A