jamieiles / 80x86

80186 compatible SystemVerilog CPU core and FPGA reference design

jamieiles
jamieiles
Date Created 2017-07-24 (7 years ago)
Commits 1,235 (last one about a year ago)
Stargazers 389 (0 this week)
Watchers 25 (0 this week)
Forks 54
License gpl-3.0
Ranking

RepositoryStats indexes 632,894 repositories, of these jamieiles/80x86 is ranked #114,615 (82nd percentile) for total stargazers, and #86,822 for total watchers. Github reports the primary language for this repository as C++, for repositories using this language it is ranked #6,376/33,733.

jamieiles/80x86 is also tagged with popular topics, for these it's ranked: fpga (#89/515),  x86 (#87/290)

Other Information

jamieiles/80x86 has Github issues enabled, there are 8 open issues and 2 closed issues.

Homepage URL: https://www.jamieiles.com/80186/

Star History

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

2 commits on the default branch (master) since jan '22

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Issue History

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Languages

The primary language is C++ but there's also others...

C++C++SystemVerilogSystemVerilogPythonPythonCMakeCMakeCCVerilogVerilogAssemblyAssemblyShellShellTclTclDockerfileDockerfileOtherOther

updated: 2025-03-16 @ 06:25am, id: 98195468 / R_kgDOBdpYDA