calint / tang-nano-9k--riscv--cache-psram

RISC-V implementation of RV32I for FPGA board Tang Nano 9K utilizing on-board burst PSRAM, flash and SD card

calint
calint
Date Created 2024-06-17 (9 months ago)
Commits 898 (last one a day ago)
Stargazers 28 (0 this week)
Watchers 2 (0 this week)
Forks 1
License unknown
Ranking

RepositoryStats indexes 631,351 repositories, of these calint/tang-nano-9k--riscv--cache-psram is ranked #609,473 (3rd percentile) for total stargazers, and #480,831 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #188/195.

calint/tang-nano-9k--riscv--cache-psram is also tagged with popular topics, for these it's ranked: risc-v (#275/281)

Other Information

There have been 24 releases, the latest one was published on 2025-03-20 (5 days ago) with the name 1.1.14.

Star History

Github stargazers over time

303025252020151510105500Jul '24Jul '24Aug '24Aug '24Sep '24Sep '24Oct '24Oct '24Nov '24Nov '24Dec '24Dec '2420252025Feb '25Feb '25Mar '25Mar '25

Watcher History

Github watchers over time, collection started in '23

3333222222111124 Feb24 FebMar '25Mar '2508 Mar08 Mar16 Mar16 Mar24 Mar24 Mar

Recent Commit History

898 commits on the default branch (main) since jan '22

90090080080070070060060050050040040030030020020010010000Jul '24Jul '24Aug '24Aug '24Sep '24Sep '24Oct '24Oct '24Nov '24Nov '24Dec '24Dec '2420252025Feb '25Feb '25Mar '25Mar '25

Yearly Commits

Commits to the default branch (main) per year

6006005005004004003003002002001001000020242024

Issue History

No issues have been posted

Languages

The primary language is SystemVerilog but there's also others...

SystemVerilogSystemVerilogC++C++AssemblyAssembly

updated: 2025-03-23 @ 08:10pm, id: 816284870 / R_kgDOMKeExg