Trending repositories for topic vhdl
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
Package manager and build abstraction tool for FPGA/ASIC development
An open-source HDL register code generator fast enough to run in real time.
An open-source HDL register code generator fast enough to run in real time.
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Package manager and build abstraction tool for FPGA/ASIC development
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Package manager and build abstraction tool for FPGA/ASIC development
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem
An open-source HDL register code generator fast enough to run in real time.
An open-source HDL register code generator fast enough to run in real time.
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
IEEE 754 single and double precision floating point library in systemverilog and vhdl
Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
VS Code based debugger for hardware designs in Amaranth or Verilog
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
Tutorials centred around Gowin FPGA parts for the /r/GowinFPGA subreddit
A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
An open-source HDL register code generator fast enough to run in real time.
VS Code based debugger for hardware designs in Amaranth or Verilog
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Package manager and build abstraction tool for FPGA/ASIC development
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
A List of Free and Open Source Hardware Verification Tools and Frameworks
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
VS Code based debugger for hardware designs in Amaranth or Verilog
I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has ...
This repository hosts the code for an FPGA based accelerator for convolutional neural networks
📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
Image Processing Toolbox in Verilog using Basys3 FPGA
IEEE 754 single and double precision floating point library in systemverilog and vhdl
:key: Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.
Tutorials centred around Gowin FPGA parts for the /r/GowinFPGA subreddit