Trending repositories for topic vhdl

Digital logic design tool and simulator

VHDL 2008/93/87 simulator

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

A FPGA friendly 32 bit RISC-V CPU implementation

Package manager and build abstraction tool for FPGA/ASIC development

:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Scala based HDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

VHDL 2008/93/87 simulator

Digital logic design tool and simulator

Package manager and build abstraction tool for FPGA/ASIC development

A FPGA friendly 32 bit RISC-V CPU implementation

:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Scala based HDL

Digital logic design tool and simulator

A FPGA friendly 32 bit RISC-V CPU implementation

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

Haskell to VHDL/Verilog/SystemVerilog compiler

Scala based HDL

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

VHDL 2008/93/87 simulator

No description

VUnit is a unit testing framework for VHDL/SystemVerilog

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has ...

Code generation tool for control and status registers

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

Package manager and build abstraction tool for FPGA/ASIC development

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has ...

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

No description

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

Code generation tool for control and status registers

Digital logic design tool and simulator

VUnit is a unit testing framework for VHDL/SystemVerilog

:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

A FPGA friendly 32 bit RISC-V CPU implementation

Haskell to VHDL/Verilog/SystemVerilog compiler

Scala based HDL

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

VHDL 2008/93/87 simulator

Package manager and build abstraction tool for FPGA/ASIC development

Digital logic design tool and simulator

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

A FPGA friendly 32 bit RISC-V CPU implementation

VHDL 2008/93/87 simulator

:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Scala based HDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

Hardware Description Languages

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

Haskell to VHDL/Verilog/SystemVerilog compiler

Package manager and build abstraction tool for FPGA/ASIC development

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

A List of Free and Open Source Hardware Verification Tools and Frameworks

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

VUnit is a unit testing framework for VHDL/SystemVerilog

A huge VHDL library for FPGA development

No description

A simple RISC-V processor for use in FPGA designs.

Code generation tool for control and status registers

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

VHDL Guide

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has ...

IEEE 754 floating point library in system-verilog and vhdl

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

VHDL course at Brno University of Technology

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

Image Processing Toolbox in Verilog using Basys3 FPGA

Tutorials centred around Gowin FPGA parts for the /r/GowinFPGA subreddit

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

A huge VHDL library for FPGA development

A simple RISC-V processor for use in FPGA designs.

Digital logic design tool and simulator

No description

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

A bit-serial CPU written in VHDL, with a simulator written in C.

Code generation tool for control and status registers

:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Hardware Description Languages

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

Digital logic design tool and simulator

A FPGA friendly 32 bit RISC-V CPU implementation

VHDL 2008/93/87 simulator

:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

Scala based HDL

Hardware Description Languages

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Package manager and build abstraction tool for FPGA/ASIC development

A List of Free and Open Source Hardware Verification Tools and Frameworks

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

A modern and open-source cross-platform software for chips reverse engineering.

Haskell to VHDL/Verilog/SystemVerilog compiler

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

A tiny Open POWER ISA softcore written in VHDL 2008

VHDL compiler and simulator

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

Code generation tool for control and status registers

No description

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has ...

Open source FPGA development platform

A modern and open-source cross-platform software for chips reverse engineering.

🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

VHDL Guide

A bit-serial CPU written in VHDL, with a simulator written in C.

Portable HyperRAM controller

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

:key: Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.

This repository hosts the code for an FPGA based accelerator for convolutional neural networks

Image Processing Toolbox in Verilog using Basys3 FPGA

AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

IEEE 754 floating point library in system-verilog and vhdl

A List of Free and Open Source Hardware Verification Tools and Frameworks

VHDL course at Brno University of Technology

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.

Tutorials centred around Gowin FPGA parts for the /r/GowinFPGA subreddit

VHDL code for using Xilnx LVDS lines for MIPI CSI-2 TX protocol. For educational purposes

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.