chipsalliance / verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Date Created 2019-11-07 (4 years ago)

Commits 3,685 (last one a day ago)

Stargazers 1,242 (3 this week)

Watchers 50 (0 this week)

Forks 195

License other

Ranking

RepositoryStats indexes 528,822 repositories, of these chipsalliance/verible is ranked #39,384 (93rd percentile) for total stargazers, and #40,879 for total watchers. Github reports the primary language for this repository as C++, for repositories using this language it is ranked #2,052/28,451.

chipsalliance/verible is also tagged with popular topics, for these it's ranked: hacktoberfest (#2,037/14017), parser (#111/1120), productivity (#105/580), linter (#80/432), analysis (#45/373), language-server-protocol (#27/139)

Other Information

chipsalliance/verible has 29 open pull requests on Github, 961 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 451 open issues and 478 closed issues.

There have been 973 releases, the latest one was published on 2024-06-11 (a day ago)

Homepage URL: https://chipsalliance.github.io/verible/

All Topics

yacc lexer linter parser sv-lrm verible analysis formatter lsp-server syntax-tree productivity style-linter hacktoberfest systemverilog systemverilog-parser systemverilog-developer language-server-protocol

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

1,889 commits on the default branch (master) since jan '22

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Commits to the default branch (master) per year

Issue History

Languages

The primary language is C++ but there's also others...

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updated: 2024-06-12 @ 12:30am, id: 220114000 / R_kgDODR6sUA